HLS-pg: High-Level Synthesis of Power-Gated Circuits

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A problem inherent in power-gated circuits is the overhead of state-retention storage required to preserve the circuit state in standby mode. HLS-pg is a new design framework that takes power gating into account, from scheduling, allocation, and controller synthesis to the final circuit layout. Its main feature is a new scheduler that minimizes the number of retention registers required at the power-gating control step. In experiments on benchmark designs implemented in 0.9-V 65-nm technology, HLS-pg reduced leakage current by 20.7% on average, with 5.0% less area and 4.1% less wirelength, compared to the power-gated circuits produced by conventional high-level synthesis.
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Issue Date
2009-03
Language
English
Article Type
Article
Citation

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, v.28, no.3, pp.451 - 456

ISSN
0278-0070
DOI
10.1109/TCAD.2009.2013283
URI
http://hdl.handle.net/10203/99361
Appears in Collection
EE-Journal Papers(저널논문)
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