DC Field | Value | Language |
---|---|---|
dc.contributor.author | Park, Chanik | ko |
dc.contributor.author | Cheon, Wonmoon | ko |
dc.contributor.author | Kang, Jeonguk | ko |
dc.contributor.author | Roh, Kangho | ko |
dc.contributor.author | Cho, Wonhee | ko |
dc.contributor.author | Kim, Jin-Soo | ko |
dc.date.accessioned | 2013-03-06T21:19:09Z | - |
dc.date.available | 2013-03-06T21:19:09Z | - |
dc.date.created | 2012-02-06 | - |
dc.date.created | 2012-02-06 | - |
dc.date.issued | 2008-07 | - |
dc.identifier.citation | ACM TRANSACTIONS ON EMBEDDED COMPUTING SYSTEMS, v.7, no.4 | - |
dc.identifier.issn | 1539-9087 | - |
dc.identifier.uri | http://hdl.handle.net/10203/88495 | - |
dc.description.abstract | In this article, a novel FTL (flash translation layer) architecture is proposed for NAND flash-based applications such as MP3 players, DSCs (digital still cameras) and SSDs (solid- state drives). Although the basic function of an FTL is to translate a logical sector address to a physical sector address in flash memory, efficient algorithms of an FTL have a significant impact on performance as well as the lifetime. After the dominant parameters that affect the performance and endurance are categorized, the design space of the FTL architecture is explored based on a diverse workload analysis. With the proposed FTL architectural framework, it is possible to decide which configuration of FTL mapping parameters yields the best performance, depending on the differing characteristics of various NAND flash-based applications. | - |
dc.language | English | - |
dc.publisher | ASSOC COMPUTING MACHINERY | - |
dc.title | A reconfigurable FTL (flash translation layer) architecture for NAND flash-based applications | - |
dc.type | Article | - |
dc.identifier.wosid | 000259432400002 | - |
dc.identifier.scopusid | 2-s2.0-49449099545 | - |
dc.type.rims | ART | - |
dc.citation.volume | 7 | - |
dc.citation.issue | 4 | - |
dc.citation.publicationname | ACM TRANSACTIONS ON EMBEDDED COMPUTING SYSTEMS | - |
dc.identifier.doi | 10.1145/1376804.1376806 | - |
dc.contributor.localauthor | Kim, Jin-Soo | - |
dc.contributor.nonIdAuthor | Park, Chanik | - |
dc.contributor.nonIdAuthor | Cheon, Wonmoon | - |
dc.contributor.nonIdAuthor | Kang, Jeonguk | - |
dc.contributor.nonIdAuthor | Roh, Kangho | - |
dc.contributor.nonIdAuthor | Cho, Wonhee | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | flash memory | - |
dc.subject.keywordAuthor | FTL | - |
dc.subject.keywordAuthor | reconfigurable architecture | - |
dc.subject.keywordAuthor | performance analysis | - |
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.