DC Field | Value | Language |
---|---|---|
dc.contributor.author | Lyuh, CG | ko |
dc.contributor.author | Kim, Taewhan | ko |
dc.contributor.author | Kim, KW | ko |
dc.date.accessioned | 2013-03-04T07:55:52Z | - |
dc.date.available | 2013-03-04T07:55:52Z | - |
dc.date.created | 2012-02-06 | - |
dc.date.created | 2012-02-06 | - |
dc.date.issued | 2004-01 | - |
dc.identifier.citation | IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, v.23, no.1, pp.157 - 164 | - |
dc.identifier.issn | 0278-0070 | - |
dc.identifier.uri | http://hdl.handle.net/10203/82076 | - |
dc.description.abstract | Ultra-deep submicron technology and system-on-chip have resulted in a considerable portion of power dissipated on buses, in which the major sources of the power dissipation are: 1) the self transition activities on the signal lines and 2) the coupled transition activities of the lines. However, there has been no easy way of optimizing 1 and 2 simultaneously at an early stage of the synthesis process. In this paper, we propose a new (on-chip) bus synthesis algorithm to minimize the total sum of 1 and 2 in the microarchitecture synthesis. Specifically, unlike the previous approaches in which 1 and 2 are minimized sequentially without any interaction between them, or only one of them is minimized, we, given a scheduled datallow graph to be synthesized, minimize 1 and 2 simultaneously by formulating and solving the two important issues in an integrated fashion: binding data transfers to buses and determining a (physical) order of signal lines in each bus, both of which are the most critical factors that affect the results of 1 and 2. Experimental results on a number of benchmark problems show that the proposed integrated low-power bus synthesis algorithm reduces power consumption by 24.8%, 40.3%, and 18.1% on average over those in (Chang and Pedram 1995, for minimizing 1 only), (Shin and Sakurai 2001, for 2 only) and (Shin and Sakurai 2001 and Chang and Pegram 1995, for 1 and then 2), respectively. | - |
dc.language | English | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.subject | POWER | - |
dc.subject | SYSTEMS | - |
dc.subject | ENERGY | - |
dc.title | Coupling-aware high-level interconnect synthesis | - |
dc.type | Article | - |
dc.identifier.wosid | 000187573200015 | - |
dc.identifier.scopusid | 2-s2.0-0346500588 | - |
dc.type.rims | ART | - |
dc.citation.volume | 23 | - |
dc.citation.issue | 1 | - |
dc.citation.beginningpage | 157 | - |
dc.citation.endingpage | 164 | - |
dc.citation.publicationname | IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS | - |
dc.identifier.doi | 10.1109/TCAD.2003.819892 | - |
dc.contributor.localauthor | Kim, Taewhan | - |
dc.contributor.nonIdAuthor | Lyuh, CG | - |
dc.contributor.nonIdAuthor | Kim, KW | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | coupling capacitance | - |
dc.subject.keywordAuthor | high-level synthesis | - |
dc.subject.keywordAuthor | interconnect synthesis | - |
dc.subject.keywordAuthor | power optimization | - |
dc.subject.keywordPlus | POWER | - |
dc.subject.keywordPlus | SYSTEMS | - |
dc.subject.keywordPlus | ENERGY | - |
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