Fast Floating-Point Normalisation Unit Realised Using NOR Planes
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | k.-n. han | ko |
| dc.contributor.author | s.-w. han | ko |
| dc.contributor.author | e.yoon | ko |
| dc.date.accessioned | 2013-03-03T23:11:58Z | - |
| dc.date.available | 2013-03-03T23:11:58Z | - |
| dc.date.created | 2012-02-06 | - |
| dc.date.created | 2012-02-06 | - |
| dc.date.issued | 2002-08 | - |
| dc.identifier.citation | ELECTRONICS LETTERS, v.38, no.16, pp.857 - 858 | - |
| dc.identifier.issn | 0013-5194 | - |
| dc.identifier.uri | http://hdl.handle.net/10203/80866 | - |
| dc.description.abstract | A new floating-point (FP) normalisation unit scheme is presented, that achieves enhanced performance by merging a leading zero counter (LZC) and a normalisation shifter. The LZC and the shift decoder are combined by using NOR planes to generate control signals directly to the normalisation shifter. The chip has been fabricated with a five-metal 0.18 mum CMOS process and performs the 64 bit FP normalisation within 1.4 ns. | - |
| dc.language | English | - |
| dc.publisher | Inst Engineering Technology-Iet | - |
| dc.title | Fast Floating-Point Normalisation Unit Realised Using NOR Planes | - |
| dc.type | Article | - |
| dc.identifier.wosid | 000177644200010 | - |
| dc.identifier.scopusid | 2-s2.0-0036683794 | - |
| dc.type.rims | ART | - |
| dc.citation.volume | 38 | - |
| dc.citation.issue | 16 | - |
| dc.citation.beginningpage | 857 | - |
| dc.citation.endingpage | 858 | - |
| dc.citation.publicationname | ELECTRONICS LETTERS | - |
| dc.contributor.localauthor | e.yoon | - |
| dc.contributor.nonIdAuthor | k.-n. han | - |
| dc.contributor.nonIdAuthor | s.-w. han | - |
| dc.type.journalArticle | Article | - |
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