Browse "School of Computing(전산학부)" by Author Hong, Seokin
Showing results 1 to 14 of 14
| A Low-Cost Mechanism Exploiting Narrow-Width Values for Tolerating Hard Faults in ALU Hong, Seokin; Kim, Soontae, IEEE TRANSACTIONS ON COMPUTERS, v.64, no.9, pp.2433 - 2446, 2015-09 |
| AVICA: An Access-time Variation Insensitive L1 Cache Architecture Hong, Seokin; Kim, Soontae, 2013 Design Automation and Test in Europe Conference(DATE), pp.65 - 70, European Design and Automation Association (EDAA), 2013-03-19 |
| CID: Co-Architecting Instruction Cache and Decompression System for Embedded Systems Kim, Jinkwon; Hong, Seokin; Hong, Jeongkyu; Kim, Soontae, IEEE TRANSACTIONS ON COMPUTERS, v.70, no.7, pp.1132 - 1145, 2021-07 |
| Designing a Resilient L1 Cache Architecture to Process Variation-Induced Access-Time Failures Hong, Seokin; Kim, Soontae, IEEE TRANSACTIONS ON COMPUTERS, v.65, no.10, pp.2999 - 3012, 2016-10 |
| Ensuring Cache Reliability and Energy Scaling at Near-Threshold Voltage With Macho Mahmood, Tayyeb; Hong, Seokin; Kim, Soon-Tae, IEEE TRANSACTIONS ON COMPUTERS, v.64, no.6, pp.1694 - 1706, 2015-06 |
| Interpage-Based Endurance-Enhancing Lower State Encoding for MLC and TLC Flash Memory Storages Lee, Wonyoung; Kang, Mincheol; Hong, Seokin; Kim, Soontae, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.27, no.9, pp.2033 - 2045, 2019-09 |
| Lizard: Energy-efficient hard fault detection, diagnosis and isolation in the ALU Hong, Seokin; Kim, Soontae, 28th IEEE International Conference on Computer Design, ICCD 2010, pp.342 - 349, 2010-10-03 |
| Macho: A Failure Model-oriented Adaptive Cache Architecture to enable Near-Threshold Voltage Scaling Tayyeb Mahmood; Kim, Soontae; Hong, Seokin, IEEE International Symposium on High Performance Computer Architecture , pp.532 - 541, IEEE Computer Society, 2013-02-27 |
| Partial Row Activation for Low-Power DRAM System Lee, Yebin; Kim, Hyeonggyu; Hong, Seokin; Kim, Soontae, IEEE International Symposium on High Performance Computer Architecture, pp.217 - 228, IEEE Computer Society, 2017-02-06 |
| Skinflint DRAM System: Minimizing DRAM Chip Writes for Low Power Lee, Yebin; Kim, Soontae; Hong, Seokin; Lee, Jongmin, IEEE International Symposium on High Performance Computer Architecture , pp.25 - 34, IEEE Computer Society, 2013-02-23 |
| TEPS: Transient error protection utilizing sub-word parallelism Hong, Seokin; Kim, Soontae, 2009 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2009, pp.286 - 291, 2009-05-14 |
| Ternary Cache: Three-valued MLC STT-RAM Caches Hong, Seokin; Lee, Jongmin; Kim, Soontae, IEEE International Conference on Computer Design, IEEE Circuits and Systems Society, 2014-10-20 |
| TLB Index-based Tagging for Cache Energy Reduction Lee, Jongmin; Hong, Seokin; Kim, Soontae, ACM/IEEE International Symposium on Low Power Electronics and Design, pp.85 - 90, IEEE-CAS and ACM-SIGDA, 2011-08-01 |
| Toward reliable microprocessors in nanometer-scale technologies = 나노스케일 공정에서의 고신뢰성 마이크로프로세서 설계 기법link Hong, Seokin; 홍석인; et al, 한국과학기술원, 2015 |
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