DC Field | Value | Language |
---|---|---|
dc.contributor.author | Junhyung Um | ko |
dc.contributor.author | Taewhan Kim | ko |
dc.date.accessioned | 2013-03-03T15:32:03Z | - |
dc.date.available | 2013-03-03T15:32:03Z | - |
dc.date.created | 2012-02-06 | - |
dc.date.created | 2012-02-06 | - |
dc.date.issued | 2001-03 | - |
dc.identifier.citation | IEEE TRANSACTIONS ON COMPUTERS, v.50, no.3, pp.215 - 233 | - |
dc.identifier.issn | 0018-9340 | - |
dc.identifier.uri | http://hdl.handle.net/10203/79252 | - |
dc.description.abstract | Carry-save-adder (CSA) is one of the most widely used components for fast arithmetic in industry. This paper provides a solution to the problem of finding an optimal-timing allocation of CSAs in arithmetic circuits. Namely, we present a polynomial time algorithm which finds an optimal-timing CSA allocation for a given arithmetic expression. We then extend our result for CSA allocation to the problem of optimizing arithmetic expressions across the boundary of design hierarchy by introducing a new concept, called auxiliary ports. Our algorithm can be used to carry out the CSA allocation step optimally and automatically and this can be done within the context of a standard RTL synthesis environment. | - |
dc.language | English | - |
dc.publisher | IEEE Computer Soc | - |
dc.subject | PARALLEL MULTIPLIERS | - |
dc.subject | ALGORITHM | - |
dc.title | An Optimal Allocation of Carry-Save-Adders in Arithmetic Circuits | - |
dc.type | Article | - |
dc.identifier.wosid | 000167616300003 | - |
dc.identifier.scopusid | 2-s2.0-0035272390 | - |
dc.type.rims | ART | - |
dc.citation.volume | 50 | - |
dc.citation.issue | 3 | - |
dc.citation.beginningpage | 215 | - |
dc.citation.endingpage | 233 | - |
dc.citation.publicationname | IEEE TRANSACTIONS ON COMPUTERS | - |
dc.contributor.localauthor | Taewhan Kim | - |
dc.contributor.nonIdAuthor | Junhyung Um | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | carry-save-addition | - |
dc.subject.keywordAuthor | arithmetic circuits | - |
dc.subject.keywordAuthor | VLSI | - |
dc.subject.keywordPlus | PARALLEL MULTIPLIERS | - |
dc.subject.keywordPlus | ALGORITHM | - |
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