Low power clock generator based on area-reduced interleaved synchronous mirror delay

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A new interleaved synchronous mirror delay (SMD) is proposed to reduce circuit size. In addition. the proposed interleaved SMD solves the polarity problem with just One extra inverter, Simulation results show that about 30% power reduction and 40% area reduction are achieved in the proposed interleaved SMD.
Publisher
IEE-INST ELEC ENG
Issue Date
2002-04
Language
English
Article Type
Article
Citation

ELECTRONICS LETTERS, v.38, no.9, pp.399 - 400

ISSN
0013-5194
URI
http://hdl.handle.net/10203/78486
Appears in Collection
EE-Journal Papers(저널논문)
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