Comments on the Originality of the Paper, ``The Integrated Scheduling and Allocation of High-Level Test synthesis''

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dc.contributor.authorTaewhan Kimko
dc.date.accessioned2013-03-02T16:03:47Z-
dc.date.available2013-03-02T16:03:47Z-
dc.date.created2012-02-06-
dc.date.created2012-02-06-
dc.date.issued1999-12-
dc.identifier.citationIEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS, v.E82-A, no.12, pp.2833 - 2833-
dc.identifier.issn0916-8524-
dc.identifier.urihttp://hdl.handle.net/10203/74329-
dc.languageEnglish-
dc.publisherOxford University Press-
dc.titleComments on the Originality of the Paper, ``The Integrated Scheduling and Allocation of High-Level Test synthesis''-
dc.typeArticle-
dc.type.rimsART-
dc.citation.volumeE82-A-
dc.citation.issue12-
dc.citation.beginningpage2833-
dc.citation.endingpage2833-
dc.citation.publicationnameIEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS-
dc.contributor.localauthorTaewhan Kim-
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