A nano-structure memory with SOI edge channel

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dc.contributor.authorPark, Gko
dc.contributor.authorHan, Sko
dc.contributor.authorHwang, Tko
dc.contributor.authorShin, Hyung-Cheolko
dc.date.accessioned2013-02-28T05:24:44Z-
dc.date.available2013-02-28T05:24:44Z-
dc.date.created2012-02-06-
dc.date.created2012-02-06-
dc.date.issued1999-12-
dc.identifier.citationJOURNAL OF THE KOREAN PHYSICAL SOCIETY, v.35, pp.S1003 - S1006-
dc.identifier.issn0374-4884-
dc.identifier.urihttp://hdl.handle.net/10203/72993-
dc.description.abstractWe fabricated nano structure memory with SOI edge channel and a nano dot. The width of the edge channel was determined by the thickness of the recessed top-silicon layer of Silicon-On-Insulator (SOI) wafer and the size of the sidewall nano dot was determined by the Reactive Ion Etching (RIE) and E-Beam lithography. The memory has a threshold voltage shift of about 1 V for maximum programming voltage of 7 V and showed reasonable retention and endurance characteristics.-
dc.languageEnglish-
dc.publisherKOREAN PHYSICAL SOC-
dc.subjectROOM-TEMPERATURE OPERATION-
dc.subjectSINGLE-ELECTRON MEMORY-
dc.subjectGATE-
dc.titleA nano-structure memory with SOI edge channel-
dc.typeArticle-
dc.identifier.wosid000084389800064-
dc.type.rimsART-
dc.citation.volume35-
dc.citation.beginningpageS1003-
dc.citation.endingpageS1006-
dc.citation.publicationnameJOURNAL OF THE KOREAN PHYSICAL SOCIETY-
dc.contributor.localauthorShin, Hyung-Cheol-
dc.contributor.nonIdAuthorPark, G-
dc.contributor.nonIdAuthorHan, S-
dc.contributor.nonIdAuthorHwang, T-
dc.type.journalArticleArticle; Proceedings Paper-
dc.subject.keywordPlusROOM-TEMPERATURE OPERATION-
dc.subject.keywordPlusSINGLE-ELECTRON MEMORY-
dc.subject.keywordPlusGATE-
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