Decomposition of Bus-Inverted Coding for Low-Power I/O

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dc.contributor.authorHong, Sungpackko
dc.contributor.authorKim, Taewhanko
dc.contributor.authorNarayanan, Unniko
dc.contributor.authorChung, Ki-Seokko
dc.date.accessioned2013-02-27T22:39:45Z-
dc.date.available2013-02-27T22:39:45Z-
dc.date.created2012-02-06-
dc.date.created2012-02-06-
dc.date.issued2000-
dc.identifier.citationJOURNAL OF CIRCUITS, SYSTEMS AND COMPUTERS, v.10, no.1, pp.101 - 111-
dc.identifier.issn0218-1266-
dc.identifier.urihttp://hdl.handle.net/10203/71259-
dc.description.abstractThis paper proposes a new bus-invert coding scheme for reducing the number of bus transitions. Unlike the previous schemes in which the entire bus lines or one subset of the bus lines are considered for bus-invert coding, in the proposed scheme, the bus lines are partitioned and each partitioned group is considered independently for bus-invert coding to maximize the effectiveness of reducing the total number of bus transitions. Experimental results show that the decomposed bus-invert coding scheme reduces the total number of bus transitions by 47.2% and 11.9% on average than those of the conventional and the partial bus-invert coding schemes respectively.-
dc.languageEnglish-
dc.publisherWorld Scientific Publishing Co-
dc.titleDecomposition of Bus-Inverted Coding for Low-Power I/O-
dc.typeArticle-
dc.identifier.wosid000090137700007-
dc.identifier.scopusid2-s2.0-0003292625-
dc.type.rimsART-
dc.citation.volume10-
dc.citation.issue1-
dc.citation.beginningpage101-
dc.citation.endingpage111-
dc.citation.publicationnameJOURNAL OF CIRCUITS, SYSTEMS AND COMPUTERS-
dc.contributor.localauthorKim, Taewhan-
dc.contributor.nonIdAuthorHong, Sungpack-
dc.contributor.nonIdAuthorNarayanan, Unni-
dc.contributor.nonIdAuthorChung, Ki-Seok-
dc.type.journalArticleArticle-
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