Power estimation method for highly correlated input sequences under realistic delay model

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dc.contributor.authorhansoo kimko
dc.contributor.authorhoon choiko
dc.contributor.authorseung ho hwnagko
dc.date.accessioned2013-02-27T20:20:07Z-
dc.date.available2013-02-27T20:20:07Z-
dc.date.created2012-02-06-
dc.date.created2012-02-06-
dc.date.created2012-02-06-
dc.date.issued1998-05-
dc.identifier.citationELECTRONICS LETTERS, v.34, no.10, pp.937 - 939-
dc.identifier.issn0013-5194-
dc.identifier.urihttp://hdl.handle.net/10203/70637-
dc.description.abstractA new power estimation method is presented which considers spatio-temporal correlations among the primary inputs as well as the glitch effect under a realistic delay model. To deal with the glitch effect, the symbolic simulation technique is employed, and to take the correlations among the primary inputs into account, the authors employ a new technique which transforms correlation information into a logic structure, called 'pre-logic.' Experimental results show that the estimation error of the proposed method is similar to 4% under a realistic delay model with highly correlated input streams.-
dc.languageEnglish-
dc.publisherInst Engineering Technology-Iet-
dc.titlePower estimation method for highly correlated input sequences under realistic delay model-
dc.typeArticle-
dc.identifier.wosid000073962000004-
dc.identifier.scopusid2-s2.0-3743053697-
dc.type.rimsART-
dc.citation.volume34-
dc.citation.issue10-
dc.citation.beginningpage937-
dc.citation.endingpage939-
dc.citation.publicationnameELECTRONICS LETTERS-
dc.contributor.localauthorseung ho hwnag-
dc.contributor.nonIdAuthorhansoo kim-
dc.contributor.nonIdAuthorhoon choi-
dc.description.isOpenAccessN-
dc.type.journalArticleArticle-
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