DC Field | Value | Language |
---|---|---|
dc.contributor.author | hansoo kim | ko |
dc.contributor.author | hoon choi | ko |
dc.contributor.author | seung ho hwnag | ko |
dc.date.accessioned | 2013-02-27T20:20:07Z | - |
dc.date.available | 2013-02-27T20:20:07Z | - |
dc.date.created | 2012-02-06 | - |
dc.date.created | 2012-02-06 | - |
dc.date.created | 2012-02-06 | - |
dc.date.issued | 1998-05 | - |
dc.identifier.citation | ELECTRONICS LETTERS, v.34, no.10, pp.937 - 939 | - |
dc.identifier.issn | 0013-5194 | - |
dc.identifier.uri | http://hdl.handle.net/10203/70637 | - |
dc.description.abstract | A new power estimation method is presented which considers spatio-temporal correlations among the primary inputs as well as the glitch effect under a realistic delay model. To deal with the glitch effect, the symbolic simulation technique is employed, and to take the correlations among the primary inputs into account, the authors employ a new technique which transforms correlation information into a logic structure, called 'pre-logic.' Experimental results show that the estimation error of the proposed method is similar to 4% under a realistic delay model with highly correlated input streams. | - |
dc.language | English | - |
dc.publisher | Inst Engineering Technology-Iet | - |
dc.title | Power estimation method for highly correlated input sequences under realistic delay model | - |
dc.type | Article | - |
dc.identifier.wosid | 000073962000004 | - |
dc.identifier.scopusid | 2-s2.0-3743053697 | - |
dc.type.rims | ART | - |
dc.citation.volume | 34 | - |
dc.citation.issue | 10 | - |
dc.citation.beginningpage | 937 | - |
dc.citation.endingpage | 939 | - |
dc.citation.publicationname | ELECTRONICS LETTERS | - |
dc.contributor.localauthor | seung ho hwnag | - |
dc.contributor.nonIdAuthor | hansoo kim | - |
dc.contributor.nonIdAuthor | hoon choi | - |
dc.description.isOpenAccess | N | - |
dc.type.journalArticle | Article | - |
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