DC Field | Value | Language |
---|---|---|
dc.contributor.author | Jong-Ho Lee | ko |
dc.contributor.author | Hyung-Cheol Shin | ko |
dc.contributor.author | Jong-June Kim | ko |
dc.contributor.author | Choon-Bae Park | ko |
dc.contributor.author | Young-June Park | ko |
dc.date.accessioned | 2013-02-27T15:53:59Z | - |
dc.date.available | 2013-02-27T15:53:59Z | - |
dc.date.created | 2012-02-06 | - |
dc.date.created | 2012-02-06 | - |
dc.date.issued | 1997-05 | - |
dc.identifier.citation | IEEE ELECTRON DEVICE LETTERS, v.18, no.5, pp.184 - 186 | - |
dc.identifier.issn | 0741-3106 | - |
dc.identifier.uri | http://hdl.handle.net/10203/69453 | - |
dc.description.abstract | A new SOI NMOSFET with a ''LOCOS-like'' shape self-aligned polgsilicon gate formed on the recessed channel region has been fabricated by a mix-and-match technology. For the first time, we developed a new scheme for implementing self-alignment in both source/drain and gate structure in recessed channel device fabrication, Symmetric source/drain doping profile was obtained and highly symmetric electrical characteristics were observed, Drain current measured from 0.3 mu m SOI devices with V-T of 0.773 V and T-ox = 7.6 nm is 360 mu A/mu m at V-GS = 3.5 V and V-DS = 2.5 V. Improved breakdown characteristics were obtained and the BVDSS (the drain voltage for 1 nA/mu m of I-D at V-GS = 0 V) of the device with L-eff = 0.3 mu m under the floating body condition was as high as 3.7 V. | - |
dc.language | English | - |
dc.publisher | IEEE-Inst Electrical Electronics Engineers Inc | - |
dc.subject | BREAKDOWN VOLTAGE | - |
dc.subject | MOSFETS | - |
dc.subject | PERFORMANCE | - |
dc.subject | RESISTANCE | - |
dc.title | Partially Depleted SOI NMOSFET's with Self-Aligned Polysilicon Gate Formed on the Recessed Channel Region | - |
dc.type | Article | - |
dc.identifier.wosid | A1997WU99600006 | - |
dc.identifier.scopusid | 2-s2.0-0031140719 | - |
dc.type.rims | ART | - |
dc.citation.volume | 18 | - |
dc.citation.issue | 5 | - |
dc.citation.beginningpage | 184 | - |
dc.citation.endingpage | 186 | - |
dc.citation.publicationname | IEEE ELECTRON DEVICE LETTERS | - |
dc.contributor.localauthor | Hyung-Cheol Shin | - |
dc.contributor.nonIdAuthor | Jong-Ho Lee | - |
dc.contributor.nonIdAuthor | Jong-June Kim | - |
dc.contributor.nonIdAuthor | Choon-Bae Park | - |
dc.contributor.nonIdAuthor | Young-June Park | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordPlus | BREAKDOWN VOLTAGE | - |
dc.subject.keywordPlus | MOSFETS | - |
dc.subject.keywordPlus | PERFORMANCE | - |
dc.subject.keywordPlus | RESISTANCE | - |
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