A New self-Aligned Offset Staggered Polysilicon Thin Film Transistor

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dc.contributor.authorjung-in hanko
dc.contributor.authorgi-young yangko
dc.contributor.authorchul-hi hanko
dc.date.accessioned2013-02-27T11:28:05Z-
dc.date.available2013-02-27T11:28:05Z-
dc.date.created2012-02-06-
dc.date.created2012-02-06-
dc.date.issued1999-08-
dc.identifier.citationIEEE ELECTRON DEVICE LETTERS, v.20, no.8, pp.381 - 383-
dc.identifier.issn0741-3106-
dc.identifier.urihttp://hdl.handle.net/10203/68270-
dc.description.abstractA new self-aligned offset staggered polysilicon thin-film transistor (poly-Si TFT) has been proposed and demonstrated to have a suppressed leakage current. For the self-aligned offset structure, planarization with thick photoresist and etchback of photoresist are successfully utilized, The offset length can be easily controlled by the thickness of the gate material without photolithographic limitation. In the self-aligned offset polysilicon TFT's, the leakage current decreases with an increasing offset length.-
dc.languageEnglish-
dc.publisherIEEE-Inst Electrical Electronics Engineers Inc-
dc.subjectTFTS-
dc.subjectGATE-
dc.titleA New self-Aligned Offset Staggered Polysilicon Thin Film Transistor-
dc.typeArticle-
dc.identifier.wosid000081791700001-
dc.identifier.scopusid2-s2.0-0344004687-
dc.type.rimsART-
dc.citation.volume20-
dc.citation.issue8-
dc.citation.beginningpage381-
dc.citation.endingpage383-
dc.citation.publicationnameIEEE ELECTRON DEVICE LETTERS-
dc.contributor.localauthorchul-hi han-
dc.contributor.nonIdAuthorjung-in han-
dc.contributor.nonIdAuthorgi-young yang-
dc.type.journalArticleArticle-
dc.subject.keywordAuthorplanarization-
dc.subject.keywordAuthorpoly-Si TFT-
dc.subject.keywordAuthorPR-
dc.subject.keywordAuthorself-aligned off-set-
dc.subject.keywordAuthorstaggered-
dc.subject.keywordPlusTFTS-
dc.subject.keywordPlusGATE-
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