A 14-b linear capacitor self-trimming pipelined ADC

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The capacitor mismatch in a 1.5-b/stage pipelined ADC is background calibrated in the analog domain using a pseudorandom (PN) dithering concept. The reference voltage added/subtracted during the normal operation is used as a dither to PN-modulate the mismatch error so that it can be embedded into the residue and be recovered later by correlating with the same PN sequence. Six MSB stages are simultaneously calibrated using separate zero-forcing feedback loops. The signal-subtracted analog PN correlation shortens the calibration time by one order. A 4.2 x 3.8 mm(2) prototype chip in 0.18-mum CMOS exhibits +/-1 LSB INL at 14 b and 84 dB SFDR at 30 MS/s, and consumes 350 mW at 3 V.
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Issue Date
2004-11
Language
English
Article Type
Article
Keywords

A/D CONVERTER; CMOS

Citation

IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.39, pp.2046 - 2051

ISSN
0018-9200
DOI
10.1109/JSSC.2004.835823
URI
http://hdl.handle.net/10203/6694
Appears in Collection
EE-Journal Papers(저널논문)
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