A Port-Oriented Space Saving Hierarchical Logic Simulator
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | 이용희 | ko |
| dc.contributor.author | 황승호 | ko |
| dc.date.accessioned | 2013-02-25T19:12:54Z | - |
| dc.date.available | 2013-02-25T19:12:54Z | - |
| dc.date.created | 2012-02-06 | - |
| dc.date.created | 2012-02-06 | - |
| dc.date.issued | 1994-06 | - |
| dc.identifier.citation | KITE JOURNAL OF ELECTRONICS ENGINEERING, v.5, no.1, pp.51 - 57 | - |
| dc.identifier.issn | 1061-3417 | - |
| dc.identifier.uri | http://hdl.handle.net/10203/64591 | - |
| dc.language | English | - |
| dc.publisher | 대한전자공학회 | - |
| dc.title | A Port-Oriented Space Saving Hierarchical Logic Simulator | - |
| dc.type | Article | - |
| dc.type.rims | ART | - |
| dc.citation.volume | 5 | - |
| dc.citation.issue | 1 | - |
| dc.citation.beginningpage | 51 | - |
| dc.citation.endingpage | 57 | - |
| dc.citation.publicationname | KITE JOURNAL OF ELECTRONICS ENGINEERING | - |
| dc.contributor.localauthor | 황승호 | - |
| dc.contributor.nonIdAuthor | 이용희 | - |
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