DC Field | Value | Language |
---|---|---|
dc.contributor.author | S.S.Lee | ko |
dc.contributor.author | S.H.Hwang | ko |
dc.date.accessioned | 2013-02-25T18:22:31Z | - |
dc.date.available | 2013-02-25T18:22:31Z | - |
dc.date.created | 2012-02-06 | - |
dc.date.created | 2012-02-06 | - |
dc.date.issued | 1993-09 | - |
dc.identifier.citation | ELECTRONICS LETTERS, v.29, no.18, pp.1625 - 1626 | - |
dc.identifier.issn | 0013-5194 | - |
dc.identifier.uri | http://hdl.handle.net/10203/64284 | - |
dc.description.abstract | A state assignment algorithm for two-level logic implementation based on a simulated annealing algorithm is proposed. To save CPU time an efficient cost estimation method is devised without losing much estimation accuracy. The experimental results based on 40 benchmark example finite state machines show that the number of cubes and area obtained by the proposed approach is approximately 10% less than that of NOVA [1] within a comparable CPU time. For a large example, it could reduce the number of product terms by more than 40%. | - |
dc.language | English | - |
dc.publisher | Inst Engineering Technology-Iet | - |
dc.subject | MACHINES | - |
dc.title | State Assignment Scheme for Two - level Logic Implementation Based on a Simulated Algorithm with a FAST Cost Estimation Method | - |
dc.type | Article | - |
dc.identifier.wosid | A1993MG40700022 | - |
dc.type.rims | ART | - |
dc.citation.volume | 29 | - |
dc.citation.issue | 18 | - |
dc.citation.beginningpage | 1625 | - |
dc.citation.endingpage | 1626 | - |
dc.citation.publicationname | ELECTRONICS LETTERS | - |
dc.contributor.localauthor | S.H.Hwang | - |
dc.contributor.nonIdAuthor | S.S.Lee | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | FINITE STATE MACHINES | - |
dc.subject.keywordAuthor | ALGORITHMS | - |
dc.subject.keywordAuthor | COMPUTER AIDED DESIGN | - |
dc.subject.keywordPlus | MACHINES | - |
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