State Assignment Scheme for Two - level Logic Implementation Based on a Simulated Algorithm with a FAST Cost Estimation Method

Cited 0 time in webofscience Cited 0 time in scopus
  • Hit : 268
  • Download : 0
DC FieldValueLanguage
dc.contributor.authorS.S.Leeko
dc.contributor.authorS.H.Hwangko
dc.date.accessioned2013-02-25T18:22:31Z-
dc.date.available2013-02-25T18:22:31Z-
dc.date.created2012-02-06-
dc.date.created2012-02-06-
dc.date.issued1993-09-
dc.identifier.citationELECTRONICS LETTERS, v.29, no.18, pp.1625 - 1626-
dc.identifier.issn0013-5194-
dc.identifier.urihttp://hdl.handle.net/10203/64284-
dc.description.abstractA state assignment algorithm for two-level logic implementation based on a simulated annealing algorithm is proposed. To save CPU time an efficient cost estimation method is devised without losing much estimation accuracy. The experimental results based on 40 benchmark example finite state machines show that the number of cubes and area obtained by the proposed approach is approximately 10% less than that of NOVA [1] within a comparable CPU time. For a large example, it could reduce the number of product terms by more than 40%.-
dc.languageEnglish-
dc.publisherInst Engineering Technology-Iet-
dc.subjectMACHINES-
dc.titleState Assignment Scheme for Two - level Logic Implementation Based on a Simulated Algorithm with a FAST Cost Estimation Method-
dc.typeArticle-
dc.identifier.wosidA1993MG40700022-
dc.type.rimsART-
dc.citation.volume29-
dc.citation.issue18-
dc.citation.beginningpage1625-
dc.citation.endingpage1626-
dc.citation.publicationnameELECTRONICS LETTERS-
dc.contributor.localauthorS.H.Hwang-
dc.contributor.nonIdAuthorS.S.Lee-
dc.type.journalArticleArticle-
dc.subject.keywordAuthorFINITE STATE MACHINES-
dc.subject.keywordAuthorALGORITHMS-
dc.subject.keywordAuthorCOMPUTER AIDED DESIGN-
dc.subject.keywordPlusMACHINES-
Appears in Collection
RIMS Journal Papers
Files in This Item
There are no files associated with this item.

qr_code

  • mendeley

    citeulike


rss_1.0 rss_2.0 atom_1.0