A low-phase noise quadrature VCO design in CMOS technology

Abstract

This thesis presents a source-injection parallel coupled (SIPC) quadrature VCO (QVCO) topology. In the proposed SIPC-QVCO, compare to the conventional parallel-coupled LC-QVCO (P-QVCO), the coupling transistors are configured in a way so that the 1/f noise, contributed by the coupling transistors at the output, can be avoided. The newly proposed SIPC-QVCO and conventional P-QVCO are fabricated based on 0.25$\mum$ CMOS technology. The phase noise of SIPC-QVCO measured at 1.5GHz shows more than 10dB improvement than that of the conventional P-QVCO over the offset frequency range of 10k~1MHz while dissipating the same amount of power.