DC Field | Value | Language |
---|---|---|
dc.contributor.advisor | Lee, Sang-Gug | - |
dc.contributor.advisor | 이상국 | - |
dc.contributor.author | Choi, Hyoung-Chul | - |
dc.contributor.author | 최형철 | - |
dc.date.accessioned | 2011-12-30 | - |
dc.date.available | 2011-12-30 | - |
dc.date.issued | 2004 | - |
dc.identifier.uri | http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=392377&flag=dissertation | - |
dc.identifier.uri | http://hdl.handle.net/10203/55293 | - |
dc.description | 학위논문(석사) - 한국정보통신대학교 : 공학부, 2004, [ iii, 39 p. ] | - |
dc.description.abstract | This thesis presents a source-injection parallel coupled (SIPC) quadrature VCO (QVCO) topology. In the proposed SIPC-QVCO, compare to the conventional parallel-coupled LC-QVCO (P-QVCO), the coupling transistors are configured in a way so that the 1/f noise, contributed by the coupling transistors at the output, can be avoided. The newly proposed SIPC-QVCO and conventional P-QVCO are fabricated based on 0.25$\mum$ CMOS technology. The phase noise of SIPC-QVCO measured at 1.5GHz shows more than 10dB improvement than that of the conventional P-QVCO over the offset frequency range of 10k~1MHz while dissipating the same amount of power. | eng |
dc.language | eng | - |
dc.publisher | 한국정보통신대학교 | - |
dc.subject | Low-Phase noise quadrature VCO design | - |
dc.subject | CMOS technology | - |
dc.title | A low-phase noise quadrature VCO design in CMOS technology | - |
dc.title.alternative | CMOS 기술을 이용한 낮은 위상잡음 특성을 갖는 4-위상 전압제어발진기 설계 | - |
dc.type | Thesis(Master) | - |
dc.identifier.CNRN | 392377/225023 | - |
dc.description.department | 한국정보통신대학교 : 공학부, | - |
dc.identifier.uid | 020024116 | - |
dc.contributor.localauthor | Lee, Sang-Gug | - |
dc.contributor.localauthor | 이상국 | - |
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