Studies on the effects of material design parameters on the board level reliabilities of wafer level chip size package (WLCSP) = 웨이퍼레벨 패키지(WLCSP)의 접합 후 신뢰성에 미치는 재료 설계 인자의 영향에 관한 연구

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Board level reliabilities are important issues for the wafer level chip size package (WLCSP), because WLCSPs are directly assembled on the boards without any protective structure in general. Nowadays, satisfying the required reliabilities for the WLCSPs has become more difficult due to the reduced feature sizes of I/Os. Therefore, it is important to understanding the effects of WLCSP material design parameters for enhancing the reliability. Among many materials for WLCSP manufacturing, three important material design parameters of solder, under-bump metallurgy (UBM) and dielectric material which support the interconnections will be focused in this study. First, the effect of solder composition on thermal and thermo-mechanical reliability was investigated. For analyzing the effect of solder composition, WLCSPs having four different solder balls of $Sn_{3.0}Ag_{0.5}Cu$, $Sn_{1.0}Ag_{0.5}Cu$, $Sn_{0.7}Cu$ and $Sn_{1.2}Ag_{0.5}Cu_{0.05}Ni$ were prepared. And These WLCSPs were mounted on ENIG and OSP finished substrates. For analyzing the interfacial reaction of the WLCSPs, assembled samples were thermally aged at $150^\circ C$ up to 1000 hours. On Cu-OSP pads, $Cu_6Sn_5$ IMCs were observed at both interfaces of solder/UBM and solder/Cu-OSP pad in all solder compositions. And after thermal aging, $Cu_3Sn$ IMC layer with Kirkendall voids were observed between the $Cu_6Sn_5$ IMC and Cu layer. The amount of these Kirkendall voids increased in low Ag contained solders. Especially, in Sn0.7Cu solder, crack caused by the thermal oxidation of Cu UBM layer was observed along the Kirkendall voids. Because smaller $Cu_6Sn_5$ IMC grains were formed on the UBM In lower Ag contained solders, thicker $Cu_3Sn$ IMC layers and larger amount of Kirkendall voids were formed in lower Ag solders. In $Sn_{1.2}Ag_{0.5}Cu_{0.05}Ni$ solder, the formation of $Cu_3Sn$ was suppressed due to Ni substitution in IMC. On ENIG pads, after thermal aging, at the solder/UBM interface, thick $(Cu,Ni)_6...
Advisors
Paik, Kyung-Wookresearcher백경욱researcher
Description
한국과학기술원 : 신소재공학과,
Publisher
한국과학기술원
Issue Date
2011
Identifier
466416/325007  / 020037038
Language
eng
Description

학위논문(박사) - 한국과학기술원 : 신소재공학과, 2011.2, [ viii, 96 p. ]

Keywords

under bump metallurgy; solder; reliability; wafer level chip size package; dielectric material; 유전재료; 하부금속층; 솔더; 신뢰성; 웨이퍼레벨패키지

URI
http://hdl.handle.net/10203/49895
Link
http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=466416&flag=dissertation
Appears in Collection
MS-Theses_Ph.D.(박사논문)
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