Showing results 1 to 4 of 4
A 0.6 V 12 b 10 MS/s Low-Noise Asynchronous SAR-Assisted Time-Interleaved SAR (SATI- SAR) ADC Kim, Wan; Hong, Hyeok-Ki; Roh, Yi-Ju; Kang, Hyun-Wook; Hwang, Sun-Il; Jo, Dong Shin; Chang, Dong-Jin; et al, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.51, no.8, pp.1826 - 1839, 2016-08 |
A 40-nm CMOS 12b 120-MS/s Nonbinary SAR-Assisted SAR ADC With Double Clock-Rate Coarse Decision Roh, Yi-Ju; Chang, Dong-Jin; Ryu, Seung-Tak, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v.67, no.12, pp.2833 - 2837, 2020-12 |
A Reusable Code-Based SAR ADC Design With CDAC Compiler and Synthesizable Analog Building Blocks Seo, Min-Jae; Roh, Yi-Ju; Chang, Dong-Jin; Kim, Wan; Kim, Ye-Dam; Ryu, Seung-Tak, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v.65, no.12, pp.1904 - 1908, 2018-12 |
Power-efficient flash ADC with complementary voltage-to-time converter Oh, Dong-Ryeol; Jo, Dong Shin; 문경준; Roh, Yi-Ju; Ryu, Seung-Tak, ELECTRONICS LETTERS, v.53, no.12, pp.772 - +, 2017-06 |
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