Browse "EE-Journal Papers(저널논문)" by Author Jung, Jaehwan
Showing results 1 to 9 of 9
| A 2.74-pJ/bit, 17.7-Gb/s Iterative Concatenated-BCH Decoder in 65-nm CMOS for NAND Flash Memory Lee, Youngjoo; Yoo, Hoyoung; Jung, Jaehwan; Jo, Jihyuck; Park, In-Cheol, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.48, no.10, pp.2531 - 2540, 2013-10 |
| Area-Efficient Approach for Generating Quantized Gaussian Noise Choi, Jaejoon; Jung, Jaehwan; Park, In-Cheol, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, v.63, no.7, pp.1005 - 1013, 2016-07 |
| Area-efficient method to approximate two minima for LDPC decoders Jung, Jaehwan; Lee, Youngjoo; Park, In-Cheol, ELECTRONICS LETTERS, v.50, no.23, pp.1701 - 1702, 2014-11 |
| Area-Efficient Multimode Encoding Architecture for Long BCH Codes Yoo, Hoyoung; Jung, Jaehwan; Jo, Jihyuck; Park, In-Cheol, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v.60, no.12, pp.872 - 876, 2013-12 |
| Efficient Parallel Architecture for Linear Feedback Shift Registers Jung, Jaehwan; Yoo, Hoyoung; Lee, Youngjoo; Park, In-Cheol, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v.62, no.11, pp.1068 - 1072, 2015-11 |
| Energy-Efficient Symmetric BC-BCH Decoder Architecture for Mobile Storages Hwang, Seokha; Moon, Seungsik; Jung, Jaehwan; Kim, Daesung; Park, In-Cheol; Ha, Jeongseok; Lee, Youngjoo, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS-I: REGULAR PAPERS, v.66, no.11, pp.4462 - 4475, 2019-11 |
| Energy-Scalable 4KB LDPC Decoding Architecture for NAND-Flash-Based Storage Systems Lee, Youngjoo; Jung, Jaehwan; Park, In-Cheol, IEICE TRANSACTIONS ON ELECTRONICS, v.E99C, no.2, pp.293 - 301, 2016-02 |
| Low-Complexity Tree Architecture for Finding the First Two Minima Lee, Youngjoo; Kim, Bongjin; Jung, Jaehwan; Park, In-Cheol, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v.62, no.1, pp.61 - 64, 2015-01 |
| Multi-Bit Flipping Decoding of LDPC Codes for NAND Storage Systems Jung, Jaehwan; Park, In-Cheol, IEEE COMMUNICATIONS LETTERS, v.21, no.5, pp.979 - 982, 2017-05 |
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