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| NO | Title, Author(s) (Publication Title, Volume Issue, Page, Issue Date) |
|---|---|
| GANPU: A 135TFLOPS/W Multi-DNN Training Processor for GANs with Speculative Dual-Sparsity Exploitation Kang, Sanghoon; Yoo, Hoi-Jun; Han, Donghyeon; LEE, JUHYOUNG; lM,DONGSEOK; Kim, Sangyeob; Kim, Soyeon, IEEE International Solid-State Circuits Conference, ISSCC 2020, pp.140 - 142, Institute of Electrical and Electronics Engineers Inc., 2020-02-17 | |
| A 0.22–0.89 mW Low-Power and Highly-Secure Always-on Face Recognition Processor with Adversarial Attack Prevention Kim, Youngwoo; Yoo, Hoi-Jun; Han, Donghyeon; Kim, Changhyeon, 2020 IEEE International Symposium on Circuits and Systems (ISCAS), Institute of Electrical and Electronics Engineers Inc., 2020-10-21 | |
| GANPU: A Versatile Many-Core Processor for Training GAN on Mobile Devices with Speculative Dual-Sparsity Exploitation Kang, Sanghoon; Yoo, Hoi-Jun; Han, Donghyeon; LEE, JUHYOUNG; Im, DongSeok; Kim, Sangyeob; Kim, Soyeon; RYU,JUNHA, Hot Chips: A Symposium on High Performance Chips, IEEE Technical Committee on Microprocessors and Microcomputers., 2020-08-16 | |
| A 4.45 ms Low-Latency 3D Point-Cloud-Based Neural Network Processor for Hand Pose Estimation in Immersive Wearable Devices Im, DongSeok; Yoo, Hoi-Jun; Kang, Sanghoon; Han, Donghyeon; Choi, Sungpill, IEEE Symposium on VLSI Circuits, VLSI Circuits 2020, Institute of Electrical and Electronics Engineers Inc., 2020-06-16 | |
| OmniDRL: A 29.3 TFLOPS/W Deep Reinforcement Learning Processor with Dualmode Weight Compression and On-chip Sparse Weight Transposer Lee, Juhyoung; Kim, Sangyeob; Kim, Sangjin; Jo, Wooyoung; Han, Donghyeon; Lee, Jinsu; Yoo, Hoi-Jun, 35th Symposium on VLSI Circuits, VLSI Circuits 2021, Institute of Electrical and Electronics Engineers Inc., 2021-06 | |
| An Energy-Efficient GAN Accelerator with On-chip Training for Domain Specific Optimization Kim, Soyeon; Yoo, Hoi-Jun; Kang, Sanghoon; Han, Donghyeon; Kim, Sangyeob; Kim, Sangjin, 16th IEEE Asian Solid-State Circuits Conference, A-SSCC 2020, Institute of Electrical and Electronics Engineers Inc., 2020-11-09 | |
| An Energy-efficient Deep Neural Network Training Processor with Bit-slice-level Reconfigurability and Sparsity Exploitation Han, Donghyeon; Im, Dongseok; Park, Gwangtae; Kim, Youngwoo; Song, Seokchan; Lee, Juhyoung; Yoo, Hoi-Jun, IEEE Symposium on Low-Power and High-Speed Chips (IEEE COOL CHIPS), IEEE COMPUTER SOC, 2021-04 | |
| FlashMAC: An Energy-Efficient Analog-Digital Hybrid MAC with Variable Latency-Aware Scheduling Gweon, Surin; Kang, Sanghoon; Han, Donghyeon; Lee, Kyoung-Rog; Kim, Kwantae; Yoo, Hoi-Jun, 2021 IEEE Asian Solid-State Circuits Conference (A-SSCC), IEEE, 2021-11-07 |
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