FlashMAC: An Energy-Efficient Analog-Digital Hybrid MAC with Variable Latency-Aware Scheduling

Abstract

The demand for energy-efficient DNN accelerator on edge devices is rapidly increasing. Diverse approaches using analog circuits to overcome the limitations of digital logics-leakage and limited power scaling (\sim \mathrm{CV}-{DD}^{2})-have been developed. Previous works on analog MACs can be categorized according to their operation domains. The voltage domain MAC have been studied first in the field of matrix multiplier for CNN application [1]. However, it suffered from PVT variation and limited VDD scaling of analog circuits. The frequency-domain MAC [2] took advantage of low supply voltage and high throughput, but a large power consumption of the internal oscillator and its nonlinearity restrict its accuracy of computing. A delay-based MAC approach in the time-domain [3]-[5] recently drew attention because of its easy integration with digital circuits, low power consumption, and small area. However, their support for higher precision is limited and needs multiple delay lines with digital adders for precision scaling.