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| NO | Title, Author(s) (Publication Title, Volume Issue, Page, Issue Date) |
|---|---|
| Reinforcement Learning-based Auto-router considering Signal Integrity Kim, Minsu; Park, Hyunwook; Kim, Seongguk; Son, Keeyoung; Kim, Subin; Son, Kyunjune; Choi, Seonguk; Park, Gapyeol; Kim, Joungho, 29th IEEE Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2020, IEEE, 2020-10 | |
| PAM-4 based PCIe 6.0 Channel Design Optimization Method using Bayesian Optimization Kim, Jihun; Kim, Joungho; Park, Hyunwook; Kim, SeongGuk; Choi, Seonguk; Son, Keeyoung; Park, Joonsang; Kim, Haeyeon; Song, Jinwook, 30th IEEE Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2021, IEEE, 2021-10-17 | |
| Sequential Policy Network-based Optimal Passive Equalizer Design for an Arbitrary Channel of High Bandwidth Memory using Advantage Actor Critic Choi, Seonguk; Kim, Joungho; Park, Hyunwook; Son, Keeyoung; Kim, SeongGuk; Park, Joonsang; Kim, Haeyeon; Shin, TaeIn; Kim, Keunwoo, 30th IEEE Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2021, IEEE, 2021-10-17 | |
| Deep Reinforcement Learning-based Pin Assignment Optimization of BGA Packages considering Signal Integrity with Graph Representation Park, Joonsang; Kim, Joungho; Kim, SeongGuk; Son, Keeyoung; Shin, TaeIn; Park, Hyunwook; Choi, Seonguk; Kim, Haeyeon; Kim, Keunwoo, 30th IEEE Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2021, IEEE, 2021-10-17 | |
| Modeling and Analysis of System-Level Power Supply Noise Induced Jitter (PSIJ) for 4 Gbps High Bandwidth Memory (HBM) I/O Interface Shin, TaeIn; Kim, Joungho; Park, Hyunwook; Kim, Keunwoo; Kim, SeongGuk; Son, Keeyoung; Park, Gap Yeol; Park, Joonsang; Choi, Seonguk, IEEE Electrical Design of Advanced Packaging and Systems, EDAPS 2021, IEEE, 2021-12-13 | |
| Signal Integrity Design and Analysis of a Spiral Through-Silicon Via (TSV) Array Channel for High Bandwidth Memory (HBM) Kim, SeongGuk; Kim, Joungho; Shin, TaeIn; Park, Hyunwook; Lho, Daehwan; Son, Keeyoung; Kim, Keunwoo; Park, Joonsang; Choi, Seonguk; Kim, Haeyeon, IEEE Electrical Design of Advanced Packaging and Systems, EDAPS 2021, IEEE, 2021-12-13 | |
| Neural Language Model Enables Extremely Fast and Robust Routing on Interposer Kim, Minsu; Kim, Joungho; Park, Hyunwook; Choi, Seonguk; Kim, Haeyeon; Kim, SeongGuk; Son, Keeyoung; Kim, Keunwoo; Lho, Daehwan, Designcon 2021, IEEE, 2021-08-17 | |
| Deep Reinforcement Learning-based through Silicon Via (TSV) Array Design Optimization Method considering Crosstalk Kim, Keunwoo; Park, Hyunwook; Lho, Daehwan; Kim, Minsu; Son, Keeyoung; Son, Kyungjune; Kim, Seongguk; Shin, Taein; Choi, Seonguk; Kim, Joungho, 2020 IEEE Electrical Design of Advanced Packaging and Systems, EDAPS 2020, Institute of Electrical and Electronics Engineers Inc., 2020-12 |
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