Modeling and Analysis of System-Level Power Supply Noise Induced Jitter (PSIJ) for 4 Gbps High Bandwidth Memory (HBM) I/O Interface

Abstract

In this paper, for the first time, we model and analyze the impacts of parallel I/O interface factors on system-level power supply noise induced jitter (PSIJ) in 4 Gbps HBM. PSIJ is positioned as an important noise component that determines the overall chip-packaging operations. To predict the accurate PSIJ, it must be evaluated at system-level with different domains including chip domain, SI/PI domain and interface domain. Thus, through the analysis of interface factors based on the fast and accurate system-level PSIJ model, it is possible to optimize the design effectively by integrating the domains in the pre-design stage. We model the overall interface which is composed of four parts, power/ground, channel, Tx and Rx clocking circuits. Each component is modeled and integrated in the frequency domain as jitter spectrum and verified with SPICE. Finally, the impacts of each interface factor on PSIJ are analyzed as per design parameters in the parallel I/O interface for effective integrated design. The interface design parameters that can effectively reduce PSIJ are analyzed in the critical frequency range according to the interaction of interface factors. On-chip decaps of PDN and delay of Rx buffer that have a significant impact on the critical frequency range induce large PSIJ reduction.