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Showing results 1 to 14 of 14

1
A compact multi-bit flip-flop with smaller height implementation and metal-less clock routing

Seo, Jae-Woo; Jung, Jinwook; Shin, Youngsoo, SPIE Advanced Lithography, SPIE, 2018-02-28

2
A Compact Multi-Bit Flip-Flop with Smaller Height Implementation and Metal-Less Intra-Cell Routing

Seo, Jaewoo; Jung, Jinwook; Shin, Youngsoo, Conference on Design-Process-Technology Co-Optimization for Manufacturability XII, SPIE-INT SOC OPTICAL ENGINEERING, 2018-03

3
Design and optimization of multiple-mesh clock network

Shin, Youngsoo; Jung, Jinwook; Lee, Dongsoo, International Conference on Very Large Scale Integration (VLSI-SoC), , pp.171 - 176, IFIP, IEEE, 2014-10

4
Fast timing analysis of transistor-level full custom digital circuits

Lee, Jingon; Jung, Jinwook; Shin, Youngsoo, IEEE International Symposium on Circuits & Systems, Institute of Electrical and Electronics Engineers, 2018-05-27

5
Localized DNA circuit design with majority gates

Jung, Jinwook; Shin, Youngsoo, IEEE BioMedical Circuits and Systems Conference (BioCAS), pp.172 - 175, IEEE, 2016-10-17

6
Optimizing timing margin for timing closure, area, and power

Han, In-Hak; Jung, Jinwook; Shin, Youngsoo, 한국반도체학술대회, 대한전자공학회, 2016-02-22

7
OWARU: free space-aware timing-driven incremental placement

Jung, Jinwook; Nam, Gi-Joon; Reddy, Lakshmi; Jiang, Hui-Ru; Shin, Youngsoo, 35th IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2016, pp.1 - 8, Institute of Electrical and Electronics Engineers Inc., 2016-11-07

8
Pin Accessibility-Driven Cell Layout Redesign and Placement Optimization

Seo, Jaewoo; Jung, Jinwook; Kim, Sangmin; Shin, Youngsoo, 54th Annual Design Automation Conference, DAC 2017, pp.1 - 6, Institute of Electrical and Electronics Engineers Inc., 2017-06-20

9
Redundant via insertion in SADP process with cut merging and optimization

SONG, YOUNGSOO; Jung, Jinwook; Shin, Youngsoo, International Conference on Very Large Scale Integration (VLSI-SoC), IFIP, IEEE, 2017-10-24

10
Redundant via insertion in self-aligned double patterning

Song, Youngsoo; Jung, Jinwook; Shin, Youngsoo, Conference on Design-Process-Technology Co-Optimization for Manufacturability XI, SPIE, 2017-03

11
Redundant via insertion with cut optimization for self-aligned double patterning

Song, Youngsoo; Jung, Jinwook; Shin, Youngsoo, 27th Great Lakes Symposium on VLSI, GLSVLSI 2017, pp.137 - 142, Association for Computing Machinery, 2017-05-11

12
Standard cell layout design and placement optimization for TFET-based circuits

SONG, YOUNGSOO; Jung, Jinwook; Shin, Youngsoo, 2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019, Institute of Electrical and Electronics Engineers Inc., 2019-05-26

13
Timing optimization in SADP process through wire widening and double via insertion

SONG, YOUNGSOO; Jung, Jinwook; HYUN, DAIJOON; Shin, Youngsoo, SPIE Advanced Lithography, SPIE, 2018-02-28

14
Transient clock power estimation of pre-CTS netlist

Kwon, Yonghwi; Jung, Jinwook; Han, In-Hak; Shin, Youngsoo, IEEE International Symposium on Circuits & Systems, Institute of Electrical and Electronics Engineers, 2018-05-27

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