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Showing results 1 to 3 of 3

1
A 1,024-Channel, 64-Interconnect, Capacitive Neural Interface Using a Cross-Coupled Microelectrode Array and 2-Dimensional Code-Division Multiplexing

Choi, Woojun; Chen, Yiyang; Kim, Donghwan; Weaver, Sean; Schlotter, Tilman; Livanelioglu, Can; Liao, Jiawei; et al, 2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023, Institute of Electrical and Electronics Engineers Inc., 2023-06-12

2
A 4.7MHz 53 mu W Fully Differential CMOS Reference Clock Oscillator with-22dB Worst-Case PSNR for Miniaturized SoCs

Lee, Junghyup; Park, Pyoungwon; Cho, Seong-Hwan; Je, Minkyu, 2015 IEEE International Solid- State Circuits Conference, IEEE, 2015-02-23

3
A 5GHz-95dBc-Reference-Spur 9.5mW Digital Fractional-N PLL Using Reference-Multiplied Time-to-Digital Converter and Reference-Spur Cancellation in 65nm CMOS

Kim, Hyo Jun; Sang, Jinwoo; Kim, Hyunik; Jo, Youngwoo; Kim,Taeik; Park, Hojin; Cho, Seong-Hwan, 2015 IEEE International Solid-State Circuits Conference, IEEE, 2015-02-24

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