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Browse "EE-Conference Papers(학술회의논문)" by Author Cho, J.

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Showing results 1 to 20 of 20

1	A compact, low-cost, and wide-band passive equalizer design using multi-layer PCB parasitics Song, E.; Kim, J.; Kim, Joungho; Cho, J., 2010 IEEE 19th Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2010, pp.165 - 168, IEEE, 2010-10-25
2	A designated clock generation and distribution (DCGD) chip scheme for substrate noise-free 3-D stacked SiP design Lee, W.; Ryu, C.; Cho, J.; Song, E.; Kim, Joungho, 2010 Asia-Pacific Symposium on Electromagnetic Compatibility, APEMC 2010, pp.334 - 337, APEMC 2010, 2010-04-12
3	A fast and precise eye-diagram estimation method for a channel of a pair of differential microstrip lines on PCB with arbitrary terminations Cho, J.; Song, E.; Shim, J.; Shim, Y.; Kim, Joungho, 2009 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2009, 2009-12-02
4	A precise analytical eye-diagram estimation method for non-ideal high-speed channels Cho, J.; Song, E.; Shim, J.; Kim, J.; Kim, Joungho, 2009 IEEE 18th Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS '09, pp.159 - 162, IEEE, 2009-10-19
5	A through-silicon-via to active device noise coupling study for CMOS SOI technology Duan, X.; Gu, X.; Cho, J.; Kim, Joungho, 2011 61st Electronic Components and Technology Conference, ECTC 2011, pp.1791 - 1795, ECTC 2011, 2011-05-31
6	Active circuit to through silicon via (TSV) noise coupling Cho, J.; Shim, J.; Song, E.; Pak, J.S.; Lee, J.; Lee, H.; Kim, Joungho, 2009 IEEE 18th Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS '09, pp.97 - 100, IEEE, 2009-10-19
7	Analog Electronic Neuro-Chip Sets with On-Chip Learning Capability Choi, Y.K.; Cho, J.; Lee, Soo-Young, International Symposium on Bioelectronic and Molecular Electronic Devices, pp.259 - 260, 1995-11
8	Analysis of power/ground noise effect on performance degradation of analog-to-digital converter Ahn, W.; Shim, J.; Cho, J.; Shin, Mincheol; Koo, K.; Kim, Joungho, 2009 11th Electronic Packaging Technology Conference, EPTC 2009, pp.687 - 691, 123, 2009-12-09
9	Detection of subjects with higher self-reporting stress scores using heart rate variability patterns during the day Kim, Desok; Seo, Y.; Cho, J.; Cho, C.-H., 30th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, EMBS'08, v.2008, pp.682 - 685, 2008-08-20
10	Guard ring effect for Through Silicon Via (TSV) noise coupling reduction Cho, J.; Yoon, K.; Pak, J.S.; Kim, J.; Lee, J.; Lee, H.; Park, K.; et al, 2010 IEEE CPMT Symposium Japan, ICSJ10, IEEE, 2010-08-24
11	Hangeul Handwritten Character Recognition using Multilayer Perceptron Cho, J.; Lee, Soo-Young; Park, Cheol Hoon, The 3rd JCEANF(Joint Conf. exh. AI, Neural Networks, and Fuzzy Logics), pp.39 - 43, 1993-10
12	Hybrid equalizer design for 12.5 Gbps serial data transmission Song, E.; Cho, J.; Kim, Joungho, 2009 IEEE 18th Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS '09, pp.53 - 56, 2009-10-19
13	I/O power estimation and analysis of high-speed channels in Through-Silicon Via (TSV)-based 3D IC Kim, Joungho; Cho, J.; Pak, J.S.; Song, T.; Kim, J.; Lee, H.; Lee, J.; et al, 2010 IEEE 19th Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2010, pp.41 - 44, IEEE, 2010-10-25
14	Modeling and analysis of differential signal Through Silicon Via (TSV) in 3D IC Kim, J.; Pak, J.S.; Cho, J.; Lee, J.; Lee, H.; Park, K.; Kim, Joungho, 2010 IEEE CPMT Symposium Japan, ICSJ10, IEEE, 2010-08-24
15	Modular Analog Neuro-Chip Set with on-Chip Learning by Error-Backpropagation and/or Hebbian Rules Cho, J.; Choi, Y.K.; Lee, Soo-Young, International Conference on Artificial Neural Networks, pp.25 - 29, 1994-06
16	Slow wave and dielectric quasi-TEM modes of metal-insulator-semiconductor (MIS) structure through silicon via (TSV) in signal propagation and power delivery in 3D chip package Pak, Jun So; Cho, J.; Kim, J.; Lee, J.; Lee, H.; Park, K.; Kim, Joungho, 60th Electronic Components and Technology Conference, ECTC 2010, pp.667 - 672, ECTC 2010, 2010-06-01
17	Through silicon via (TSV) equalizer Kim, Joungho; Song, E.; Cho, J.; Pak, J.S.; Lee, J.; Lee, H.; Kim, J., 2009 IEEE 18th Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS '09, pp.13 - 16, 123, 2009-10-19
18	Through Silicon Via (TSV) shielding structures Cho, J.; Kim, Joungho; Song, T.; Pak, J.S.; Kim, J.; Lee, H.; Lee, J.; et al, 2010 IEEE 19th Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2010, pp.269 - 272, IEEE, 2010-10-25
19	TSV modeling and noise coupling in 3D IC Kim, Joungho; Cho, J.; Kim, J., 3rd Electronics System Integration Technology Conference, ESTC 2010, ESTC 2010, 2010-09-13
20	VLSI Implementaion of Radial Basis Fuction Network with Learning Capability Choi, Y.K.; Cho, J.; Lee, Soo-Young, International Conference on Neural Information Processing, pp.1341 - 1346, 1995-10

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