Browse "EE-Conference Papers(학술회의논문)" by Title
Showing results 501 to 520 of 22891
| A 1.5nJ/pixel Super-Resolution Enhanced FAST Corner Detection Processor for High Accuracy AR Yoo, Hoi-Jun; Park, Seongwook; Kim, Gyeonghoon; Park, Junyoung, European Solid State Circuits Conference (ESSCIRC), pp.191 - 194, IEEE, 2014-09-23 |
| A 1.5um laser package frequency-locked with a novel miniature discharge lamp Chung, Yun Chur; Derosier, RM; Presby, HM; Burrus, CA; Akai, Y; Masuda, N, Optical Fiber Communication Conference, 1992 |
| A 1.5V, 140uA CMOS ultra-low power common-gate LNA Jeong C.J.; Qu W.; Sun Y.; Yoon D.Y.; Han S.K.; Lee, Sang-Gug, 2011 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2011, IEEE, 2011-06-05 |
| A 1.67 GHz 32-bit pipelined carry-select adder using the complementary scheme Kim, Y.; Sung, K.-H.; Kim, Lee-Sup, 2002 IEEE International Symposium on Circuits and Systems, pp.I-461 - I-464, IEEE, 2002-05-26 |
| A 1.7-GHz GaN MMIC Doherty Power Amplifier using an Adaptive Bias Circuit with a Quadrature Coupler Lee, Seungkyeong; Lee, Sangmin; Hong, Songcheol, 2017 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT 2017), IEEE, 2017-09-01 |
| A 1.8 to 2.4-GHz 20mW digital-intensive RF sampling receiver with a noise-canceling bandpass low-noise amplifier in 90nm CMOS Lee, J.; Kim, J.; Cho, SeongHwan, 2010 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2010, pp.293 - 296, IEEE, 2010-05-23 |
| A 1.8dB NF 112mW single-chip diversity tuner for 2.6GHz S-DMB applications Hwang, M.-W.; Beck, S.; Min, S.; Lee, S.; Yoo, S.; Lim, K.; Jung, H.; et al, 2006 IEEE International Solid-State Circuits Conference, ISSCC, IEEE, 2006-02-06 |
| A 1.9 GHz High Dynamic Range CMOS Power Amplifier 홍성철; 박창근; 김윤석; 한정후; 이동호; 백동현, 실리콘RF집적회로 기술워크샵, pp.438 -, 2005 |
| A 1.93 TOPS/W Scalable Deep Learning/Inference Processor with Tetra-parallel MIMD Architecture for Big Data Applications Yoo, Hoi-Jun; Park, Seongwook; Bong, Kyeongryeol; Shin, Dongjoo; Lee, Jinmook; Choi, Sungpill, IEEE International Solid- State Circuits Conference, pp.80 - 81, IEEE, 2015-02-23 |
| A 1.9nJ/pixel Embedded Deep Neural Network Processor for High Speed Visual Attention in a Mobile Vision Recognition SoC Yoo, Hoi Jun; Hong, In Joon; Park, Seong Wook; Park, Jun Young, IEEE Asian Solid-State Circuits Conference(A-SSCC), pp.185 - 188, IEEE, 2015-11-10 |
| A 10 bit gray scale digital-to-analog converter with an interpolating buffer amplifier for AMLCD column drivers Lee, H.-M.; Son, Y.-S.; Jeon, Y.-J.; Jeon, J.-Y.; Lee, G.-H.; Jung, S.-C.; Cho, Gyu-Hyeong, 2007 SID International Symposium, pp.346 - 349, Society for Information Display, 2007-05-23 |
| A 10 bit piecewise linear cascade interpolation dac with loop gain ratio control Lee, Sungwoo; Kim, Kiduk; Park, Kyusung; Park, Changbyung; Lee, Byunghun; Jeon, Jinyong; Jung, Seungchul; et al, 2010 IEEE Custom Integrated Circuits Conference -CICC 2010, IEEE, 2010-09 |
| A 10 bit piecewise linear cascade interpolation DAC with loop gain ratio control Lee, S.; Kim, K.; Park, K.; Park, C.; Lee, B.; Jeon, J.; Huh, J.; et al, 32nd Annual Custom Integrated Circuits Conference - The Showcase for Circuit Design in the Heart of Silicon Valley, CICC 2010, CICC 2010, 2010-09-19 |
| A 10 Bits Modified VCC Interpolation and DVO Correction by Drain Current Injection Lee, Sungwoo; Kim, Ki-Duk; Park, Kyu-Sung; Park, Chang-Byung; Lee, Byung-Hun; Jeon, Jin-Yong; Jung, Seung-Chul; et al, 2010 SID Symposium, pp.58 - 61, Wiley, 2010-05 |
| A 10 nV/rt Hz noise level 32-channel neural impedance sensing ASIC for local activation imaging on nerve section Kim, Jong Pal; Lee, Wonseok; Suh, Junyeub; Lee, Hyungwoo; Lee, Kyuil; Ahn, Ho Young; Seo, Min-Jae; et al, 42nd Annual International Conference of the IEEE-Engineering-in-Medicine-and-Biology-Society (EMBC), pp.4012 - 4015, IEEE, 2020-07 |
| A 10-bit 300Msample/s pipelined ADC using time-interleaved SAR ADC for front-end stages Kim, Y.-H.; Lee, J.; Cho, SeongHwan, 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, ISCAS 2010, pp.4041 - 4044, IEEE, 2010-05-30 |
| A 10-bit Modified VCC Interpolation and DVO Correction Using Drain-Current Injection Cho, Gyu-Hyeong; Lee, SW; Park, GS; Kim, KD; Park, CB; Lee, BH; Jeon, JY; et al, SID 10 DIGEST, pp.58 - 61, SID 10 DIGEST, 2010-05-28 |
| A 10-bit Serial Integration-Type DAC Architecture for AMLCD Column Drivers Cho, Gyu-Hyeong; Kim, Ki-Duk; Woo, Young-Jin; Lee, Sung-Woo; Jeon, Yong-Joon; Jeon, Jin-Yong; Yang, Jun-Hyeok; et al, SID International Symposium, pp.379 - 382, 2009 |
| A 10-Phase 270MHz 5000ppm spread spectrum clock generator Lee, W.-Y.; Kim, Lee-Sup, 2008 International SoC Design Conference, ISOCC 2008, 2008-11-24 |
| A 10-uW digital signal processor with adaptive-SNR monitoring for a sub-1V digital hearing aid Yoo, J.; Kim, S.; Cho, N.; Song, S.-J.; Yoo, Hoi-Jun, ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems, pp.3361 - 3364, 2006-05-21 |
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