Browse "EE-Conference Papers(학술회의논문)" by Title
Showing results 14401 to 14420 of 22891
| Parallel execution schemes in a Petri net Chang, Won Ho; Oh, Ha Ryoung; Lee, Kwang-Hyung; Park, Kyu Ho; Kim, Myunghwan, Proceedings of the 1988 International Conference on Parallel Processing, v.1, pp.286 - 290, 1988 |
| Parallel IDMA Architecture Based on Interleaving With Replicated Subpatterns Kong, Byeong Yong; Park, In-Cheol, 2019 IEEE 53rd International Conference on Communications (ICC 2019), IEEE, 2019-05-22 |
| Parallel LDPC Decoder Implementation on GPU Based on Unbalanced Memory Coalescing Moon, Jaekyun; Kang, Soonyoung, IEEE Inernational conference on communications, IEEE, 2012-06-10 |
| Parallel Multiprocessor Simulation Using Dynamic Execution Path Prediction Kyung, CM; Chung, Moo-Kyoung; Shim, Heejun, 13th Korean Conference on Semiconductors(KCS'2006. 한국반도체학술대회), pp.129 - 130, 2006 |
| Parallel quantum-inspired genetic algorithm for combinatorial optimization problem Han, K.-H.; Park, K.-H.; Lee, C.-H.; Kim, Jong-Hwan, Congress on Evolutionary Computation 2001, pp.1422 - 1429, IEEE, 2001-05-27 |
| Parallel Simulation of Bounded Petri Nets in Single Processor Kim, Tag-Gon; Kim, Young Chan; Kwon, In Sup, SCSC, SCSC, 1999-07 |
| Parallel unravelling for simulating open quantum systems Sinayskiy, Ilya; Park, Kyungdeok; Rhee, June-Koo Kevin; Petruccione, Francesco, Quantum Techniques in Machine Learning (QTML) 2019, pp.87 - 90, KAIST, 2019-10-23 |
| Parallel VLSI Architectures for a Class of LDPC codes Moon, Jaekyun, IEEE International Symposium on Circuits and Systems, pp.0 - 0, 2005-05-15 |
| Parallel 방식을 이용한 2K/4K/8K-point FFT processor 문상철; 박인철, SOC Design Conference, 2002-10 |
| Parallelized Inverse Dynamics Algorithm for Dynamic Control of a Robot Manipulator Kim, S.D.; Roh, C.L.; Chung, Myung Jin, Proceedings of the IFAC Workshop on Algorithms and Architectures for Real-time Control, pp.49 - 53, 1992-08 |
| Parallelized List Sphere Decoder Architecture with Modified Precomputation Park, Sin Chong, ICWMMN 2006 |
| Parallelized VLSI Architecture for List Sphere Decoder Park, Sin Chong, ICACT2007 |
| Parallelized VLSI architecture of single stack based list sphere decoder Kim H.-S.; Seo S.-H.; Park, Sin Chong, 8th International Conference on Signal Processing, ICSP 2006, v.1, 2006-11-16 |
| Parallelizing garbage collection with I/O to improve flash resource utilization Choi, Wonil; Jung, Myoungsoo; Kandemir, Mahmut; Das, Chita, 27th ACM International Symposium on High-Performance Parallel and Distributed Computing, HPDC 2018, pp.243 - 254, Association for Computing Machinery, Inc, 2018-06-11 |
| Paralyzing Drones via EMI Signal Injection on Sensory Communication Channels Jang, Joonha; Cho, Mangi; Kim, Jaehoon; Kim, Dongkwan; Kim, Yongdae, 2023 Network and Distributed System Security Symposium (NDSS), Internet Society, 2023-03-01 |
| Parameter estimation and control for permanent magnet synchronous motor drive using model reference adaptive technique Kim, Kyeong-Hwa; Chung, Se-Kyo; Moon, GunWoo; Baik, In-Cheol; Youn, Myung Joong, Industrial Electronics, Control, and Instrumentation, 1995., Proceedings of the 1995 IEEE IECON 21st International Conference on, pp.387 - 392, IEEE, 1995-11-06 |
| Parameter identification for chaotic system with random noise by differential evolution algorithm Cao, Fei; Lee, Ju-Jang, 2009 World Summit on Genetic and Evolutionary Computation, World Summit on Genetic and Evolutionary Computation, 2009-08 |
| Parameter identification for the cascaded fiber optic lattice structure using the Schur algorithm Bae, J.; Kim, K.; Chun, Joohwan, Optical Devices for Fiber Communication II, pp.95 - 102, SPIE, 2000-11-06 |
| Parameter optimization of a voltage reference circuit using EP Nam Dongkyung; Seo Yun Deuk; Park Lae-Jeong; Park, Cheol Hoon; Kim Bumsup, Proceedings of the 1998 IEEE International Conference on Evolutionary Computation, ICEC'98, pp.301 - 305, IEEE, 1998-05-04 |
| Parameter Optimization using Evolutionary Programming in Voltage Regulator Design 박철훈, JCEANF'96, v.5, pp.405 - 408, 1996 |
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