This thesis proposes a novel decoding architecture to decode in real-time H.264/AVC bitstream coded in Context-based Adaptive Binary Arithmetic Coding (CABAC). The proposed architecture issues two context model sets at the same time, which leads to drastic reduction in cycles invoked by the syntax element switching overhead that degrades the decoding performance significantly. To design such an efficient architecture, a thorough investigation on the transition pattern of syntax elements has been conducted. Furthermore, the statistics on numbers of bins for a SE which implies the significance of SBS has ignited it to develop the proposed architecture. The concept of dual-fetch is realized by adding a cache named context pre-fetch buffer and a multiplexer to a conventional two-stage architecture for CABAC decoding, which leads to a slight increase in the hardware complexity while enabling it to achieve a drastic enhancement in decoding performance. To fully exploit the proposed architecture, an efficient pipeline scheduling algorithm is presented as well. As a result, the proposed architecture releases the CABAC parsing from a bottleneck in decoding H.264 bitstream by achieving a decoding performance of 1.7 cycle/bin.