CABAC (Context-based Adaptive Binary Arithmetic Coding) is an important entropy coding method for H.264/AVC. CABAC achieves significant compression enhancement while bringing greater computational complexity. The decoding of CABAC imposes a heavy performance requirement on H.264/AVC decoding system.
CABAC decoder should at least reach 100Mbps throughput to decode HD1080i@60Hz video format in real-time. To achieve this requirement, many other works exploit effective pipeline architectures although CABAC decoding process is highly sequential and has strong data dependencies which make it difficult to implement the parallel process scheme.
However, power dissipation is greatly increased and many H/W resources are needed to solve these data dependency problems in CABAC decoding. Most of other works use large size of memory or many internal registers, and they spend large amount of power for memory operation.
In this paper, we analyze the data dependency of CABAC decoding process and propose a new hardware architecture for CABAC decoding. Since the power is mostly consumed for memory operation in CABAC, effective context access scheme is surely necessary. The proposed decoder needs an operation of 1 byte memory read and write in each cycle, and uses only 459 byte context memory.
Experimental results show that the proposed CABAC decoder synthesized using 0.18um standard cell library achieves 1 bit/cycle throughput and can operate in 141MHz frequency which meets the real-time decoding requirement of HD1080i@60Hz video format. Our decoder also minimizes gate count, context memory size and power consumption for memory access to achieve this throughput.