Fast acquisition all-digital PLL using sensor assisted DCO control

Abstract

As demand for portable computing and communication devices has been increasing rapidly, the power management such as frequency scaling, is getting important. Various power management techniques require on-chip clocks to be suspended or scaled down in frequency. The fast acquisition characteristic of PLL is crucial in both cases. This thesis explores how fast acquisition is achieved in an all-digital PLL (ADPLL) while minimizing overhead in area. To minimize ADPLL frequency acquisition time the DCO control code is initially predicted for the desired output frequency. As the DCO output frequency is susceptible to process, voltage, and temperature (PVT) variations, the DCO control code predictor use PVT domain translation technique. This PVT domain translation technique monitors the PVT variations and predicts the DCO control code close to the desired output frequency. The PVT domain translation technique helps the DCO control code predictor achieve overall prediction accuracy of 95-97% over the entire operating output frequency. The PVT domain translation uses a PVT sensor that is a small delay cell chain ring oscillator. This PVT sensor achieves 40% reduction of area, since it replaces 2 inner DCOs and each occupies 20% of ADPLL area. The proposed ADPLL is implemented in a 0.25μm CMOS technology. This ADPLL operates from 105MHz to 410MHz and occupies only 0.12mm2. The ADPLL has 1 cycle frequency acquisition time with accuracy of 95%, and 2-23 cycle phase acquisition time with 4% phase error. The lock-in time becomes 3-24 cycles with 21-71ps jitter (peak-to-peak).