On-chip debugging logic synthesizer for embedded microprocessors

Abstract

This thesis presents a new on-chip debugging logic(OCDL) synthesizer. Given a processor specification, the synthesizer automatically generates an OCDL that is based on the IEEE 1149.1 JTAG architecture. The JTAG is adopted to provide not only boundary scan paths but also standard debugging mechanisms such as breakpoint setting and detection, internal state monitoring and modification, etc. Compared to the previous OCDL synthesizer that focuses only on core state examination, the generated OCDL can examine memory state as well as core state by using instruction insertion techniques. The same clock that is used for the embedded processor is directly applied to the proposed OCDL to avoid the redesign of processor-specific clock controllers and to minimize the additional delay overhead. The proposed OCDL synthesizer has been successfully applied to industrial embedded processors such as an ARM7 compatible core and a floating-point DSP core for audio applications.