(A) study of geometric dependence for BJT-based 1T-DRAM

Abstract

In conventional one transistor/one capacitor dynamic random access memory (DRAM), $\textit{Moore``s Law}$ does not apply to it because conventional DRAM manufactures face a tremendous challenge to shrink the basic memory cell area as the technology feature size continues to shrink. Capacitor-less 1T-DRAM using a floating body has been investigated as an alternative for conventional DRAM. Due to the absence of a capacitor, capacitor-less 1T-DRAM is very attractive in terms of cell size scaling. Recently, studies concerning parasitic bipolar-junction-transistor (BJT)-based capacitor-less 1T-DRAM with improvements to its retention time and current sensing margin have been reported, and this type of DRAM is considered to be a promising candidate in the replacement of conventional DRAM. However, a study of the geometric dependence for the BJT-based 1T-DRAM has not yet been undertaken. In this thesis, gate length and fin width dependence on single transistor latch were investigated for the BJT-based 1T-DRAM through experiments. The single transistor latch phenomenon was introduced as an operational principle of the BJT-based 1T-DRAM and memory performance was demonstrated. The minimum drain voltage for the activation of a parasitic lateral BJT in SOI FinFET was measured at various gate lengths and fin widths. Multiplication factor and current gain of the parasitic BJT in the SOI MOSFET are introduced as determinant factors. The experiment results clearly show that the value of the latch voltage is reduced in a shorter gate length and wider fin width device. It was found that the non-local effect retards the reduction of the $V_{latch}$ as FinFET scales down. It should be noted that the memory operation with a scaled FinFET is severely affected by the fin width reduction. Therefore, fin width should be carefully designed for reliable memory operation.