DC Field | Value | Language |
---|---|---|
dc.contributor.advisor | Kim, Choong-Ki | - |
dc.contributor.advisor | 김충기 | - |
dc.contributor.author | Koh, Yo-Hwan | - |
dc.contributor.author | 고요환 | - |
dc.date.accessioned | 2011-12-14 | - |
dc.date.available | 2011-12-14 | - |
dc.date.issued | 1989 | - |
dc.identifier.uri | http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=61364&flag=dissertation | - |
dc.identifier.uri | http://hdl.handle.net/10203/36095 | - |
dc.description | 학위논문(박사) - 한국과학기술원 : 전기 및 전자공학과, 1989.8, [ iv, 94 p. ] | - |
dc.description.abstract | A latch-free self-aligned power MOSFET and IGBT structure with a very small $n^+$source region formed by outdiffusion of phosphorus from the sidewall phosphosilicate glass (PSG) is proposed and successfully fabricated and the latch-up immunity of the IGBT with the proposed structure is also numerically investigated. In the proposed structure, the source or cathode is composed of a silicide contact which shunts the outdiffused $n^+$-source and p-body region. The fabricated power MOSFET with the mask set for a conventional device shows latch-back-free I-V characteristics and the same current capability as conventional devices for the same geometry. The negligible contact resistance of $n^+$-source-tosilicide is certified theoretically and experimentally. The experimental results clearly show the validity of the new self-aligned power MOSFET with latch-back-free operation and minimized on-resistance. The proposed IGBT which has the same fabrication sequence as the power MOSFET with the proposed structure also shows good I-V characteristics without latch-up phenomena and has an extremely low on-resistance which is less than the power MOSFET even with the moderately doped p-substrate. The on-resistance of IGBT is drastically reduced by a factor of 10 because of the conductivity modulation due to the high level injection of minority carrier. Finally, the latch-up phenomena in latch-up-free self-aligned IGBT are successfully investigated using a two-dimensional device simulator (PISCES) for various lengths of the $n^+$-region. The numerical scheme which treats the IGBT structure consisting of $n^+$-p-$n^-$-$p^+$ layer as an $n^+$-i-$p^+$ diode in conduction state shows fast convergence for the calculation of the holding voltage and the holding current. The simulated results also show that sufficient latch-up immunity is obtained when the length of the $n^+$-region is less than 1μm. In order to suppress the latch-up in IGBT, the reduction of the length of the $n^+$-reg... | eng |
dc.language | eng | - |
dc.publisher | 한국과학기술원 | - |
dc.title | Latch-free self-aligned power MOSFET and IGBT structure utilizing silicide contact technology | - |
dc.title.alternative | 실리이드 접촉을 이용한 래치현상이 없는 자기정렬된 전력MOSFET 과 IGBT 구조 | - |
dc.type | Thesis(Ph.D) | - |
dc.identifier.CNRN | 61364/325007 | - |
dc.description.department | 한국과학기술원 : 전기 및 전자공학과, | - |
dc.identifier.uid | 000835013 | - |
dc.contributor.localauthor | Kim, Choong-Ki | - |
dc.contributor.localauthor | 김충기 | - |
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