Exploring design trade-offs and cost function of programmable merged DRAM logic for video signal processing = 비디오 신호처리를 위한 프로그래머블 디램-로직 혼합칩의 설계 트레이드-오프 및 코스트 함수 연구

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In this thesis, we explored system-level design trade-offs and cost function of the programmable merged DRAM logic for video signal processing in the early design stage. In addition, we explored the speed, area, and power consumption of the programmable MDL at the pre-synthesis level. At first, we proposed the relations of the programmable merged DRAM logic parameters for real-time data-intensive signal processing. The product of multiple embedded components and operating frequencies should be greater than the product of macro block rate and the number of execution cycles in order to meet the real-time conditions. We achieved the candidate solutions in terms of the number of the embedded components and the operating frequencies for various latencies of the processing elements, embedded DRAM``s, and embedded temporal storage. The experimental results indicate that not only we can find the relations of the programmable MDL parameters, but also we can select one solution among many candidate solutions according to the design constraints. Secondly, we proposed the MDL cost function in terms of speed, area, and power and we estimated the area and power consumption of the programmable merged DRAM logic as a function of the MDL parameters. From the estimated two design constraints, we can estimate whether the design budgets are roughly met or not at early design stage. Furthermore, we can evaluate the effects of various design parameters on the system-level performance, which provides significant impact on the design trade-offs in the programmable MDL. Thirdly, we proposed a search method to get application-oriented optimal MDL parameters by the branch-and-bound algorithm. We have achieved the optimal MDL parameters in the case of cost, speed, area, and power oriented applications, respectively. The experimental results indicate that we can achieve 24.2% to 42.9% enhanced performances by the optimal MDL parameters according to the application-oriented targets. Fin...
Advisors
Kim, Lee-Supresearcher김이섭researcher
Description
한국과학기술원 : 전기및전자공학전공,
Publisher
한국과학기술원
Issue Date
2001
Identifier
169503/325007 / 000965341
Language
eng
Description

학위논문(박사) - 한국과학기술원 : 전기및전자공학전공, 2001.8, [ vi, 91 p. ]

Keywords

Design Trade-offs; Merged DRAM Logic; Cost Function; 코스트함수; 설계-트레이드오프; 디램-로직 혼합칩

URI
http://hdl.handle.net/10203/35934
Link
http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=169503&flag=dissertation
Appears in Collection
EE-Theses_Ph.D.(박사논문)
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