Research on the area efficient and high performance digital FIR filter design저면적 고성능의 디지털 FIR 필터 설계에 관한 연구

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Finite impulse response (FIR) digital filters are one of the most frequently used functions in digital signal processing. In recent digital signal processing systems, FIR filters are implemented as dedicated hardware blocks due to the demand of high throughput and low power consumption, but its hardware implementation still takes large area. In digital systems, multiplications are composed of many additions and the area overhead of digital FIR filter block can be reduced by finding an optimum adder graph which maximizes the sharing of partial sums between several multiplications. In this thesis, a digital FIR filter synthesis algorithm is proposed to reduce the area overhead of FIR filter blocks. By considering multiple adder graphs for a filter coefficient, the proposed algorithm selects an adder graph that can be maximally sharable with the remaining filter coefficients, while previous dependence-graph algorithms consider only one adder graph when implementing a filter coefficient. In addition, an addition reordering technique is proposed to derive multiple adder graphs from a seed adder graph generated by using previous dependence-graph algorithms. Experimental results show that the proposed algorithm reduces the hardware cost of FIR filters by 22% and 3.4% on average compared to the Hartely and RAGn-hybrid algorithms. This thesis also proposes a FIR filter optimization algorithm to reduce the hardware cost of FIR filter blocks. There are many feasible FIR filters which meet the given frequency response constraints and we can select a proper FIR filter which minimizes the hardware costs. Though the number of odd-positive unique values and the adder cost of each unique value affect to the hardware cost of FIR filter blocks, previous optimization algorithms considers only the adder cost of unique value. The proposed optimization algorithm considers both effect during optimization. By maximizing odd-positive value sharing between coefficients during optimiz...
Advisors
Park, In-Cheolresearcher박인철researcher
Description
한국과학기술원 : 전기 및 전자공학과,
Publisher
한국과학기술원
Issue Date
2010
Identifier
418748/325007  / 020047650
Language
eng
Description

학위논문(박사) - 한국과학기술원 : 전기 및 전자공학과, 2010.2, [ vii, 93 p. ]

Keywords

multiplierblock; FIR filter synthesis; Digital filter; filter optimization; 필터 최적화; 곱셈기; 유한응답필터 합성; 디지탈 필터

URI
http://hdl.handle.net/10203/35574
Link
http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=418748&flag=dissertation
Appears in Collection
EE-Theses_Ph.D.(박사논문)
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