A study of multi-gate nanowire structure fabrication and reliability on the condition of negative bias temperature instability

Abstract

In this dissertation, fabrication and characterization of 3-dimensional multi-gate silicon nanowire-FET (SiNAWI-FET) using a sub-5nm all-around gate FinFET for high performance logic device with consideration of current direction effects and terabit non-volatile memory device using an 8nm silicon nanowire non-volatile memory (SiNAWI-NVM) with oxide/nitride/oxide (ONO) and omega-gate structure are studied. The sub-5nm N-channel SiNAWI-FET with 1.4nm HfO2 and 3nm silicon channel shows an on-state current of 367&#61549;A/&#61549;m at VG=VD=1.0V with the off-state current of 500nA/&#61549;m, which is normalized by the channel perimeter. The sub-5nm transistor was verified by using 3-dimensional device simulations. Both N-channel and P-channel SiNAWI-FET show threshold voltage increment with a decrement of silicon channel width by quantum confinement effects. And due to the current direction effects of multi-gate silicon nanowire transistor, N- and P-channel SiNAWI-FET show the highest driving current on (110)/<110> crystal orientation without device rotation, whereas most 3-dimensional N-channel device reports higher driving current on 45o device rotation rather than 0o. The fabricated 8nm SiNAWI-NVM with 7nm spherical silicon nanowire channel and 3.8/6.4/5.1nm ONO-structure shows 1.7V VT-window from 12V/80&#61549;sec program condition. The acceptable electrical characteristics and the excellent erase efficiency of 8nm non-volatile memory with thick gate dielectric layer of ONO-structure are influence of the extremely narrow spherical silicon nanowire channel and omega-shaped gate structure by the superior gate controllability. And the silicon nanowire transistor reliability on the condition of negative bias temperature instability (NBTI) is studied using P-channel SOI and body-tied FinFETs with various fin width and substrate conditions. The NBTI is one of the concept of device reliability which is became major product level reliability challenges for the sub-6...