This thesis describes a Software Defined Radio (SDR) transceiver architecture and algorithm for WCDMA applications. SDR technology is characterized to use programmable hardware and reconfiguable software packages. Big differences with conventional transceiver are treating a wide range of frequency and wide bandwidth for analog part, and design of IF mixer with software technology. This thesis also includes a phase noise analysis for VCO design and a design of CMOS WCDMA transmitter.
Motivation is that highly integrated RF circuitry is required to design competitive mobile handsets. The RF front-end for mobile handset consists of transmitter section, receiver section, and frequency synthesis section. Recently all of these sections are studied to design with CMOS technology and SDR technology, which can provide re-useability for hardware and multi-mode operation with software reconfiguration.
VCO is most critical component for frequency synthesis. A phase noise analysis is important to design it with low phase noise characteristics.
For a RF transmitter design, it’s architecture and target specifications for functional blocks should be decided. These can be decided through a studying of system requirements, design considerations for linearity and gain control with a linear-in-dB characteristic.
For the receiver section, SDR Technology is adopted. The proposed receiver architecture is consisted of the relative simple analog part, the 80 Msamples/sec 10 bit ADC and the IQ demodulator.
Goals of this thesis are to propose a SDR architecture and algorithm, and implementing with IF band sampling ADC and IQ demodulator for multi-mode WCDMA receiver. A design method for low noise CMOS VCO and a design for CMOS WCDMA transmitter are included.
Conclusively, the proposed SDR architecture and algorithm can be adopted to design for an efficient multi mode CMOS WCDMA transceiver, because the IQ demodulator shows less than 0.5 dB implementation loss in QPSK mode, 0.6 and 1.0 d...