Design and implementation of low-power 3D graphics SoC for mobile multimedia applications

Abstract

A low-power graphics SoC implementing full-3D pipeline with texture-mapping and special rendering effects is designed for mobile multimedia applications such as PDAs or cell-phones. The chip contains a RISC processor with MAC as a geometry engine, a 3D rendering engine, a programmable power optimizer, and 29Mb embedded DRAM. Low-power consumption is achieved by applying various techniques to the instruction set architecture, pipeline structure, shading and texturing datapath, memory architecture, clock control, and embedded DRAM. Programmable clocking allows the chip to operate in lower power modes for various applications. The chip consumes less than 210mW, delivering 1Mvertices/s, 66Mpixels/s and 264Mtexle/s texture-mapped pixels with real-time special effects. The 121㎟ chip is fabricated with 0.16um 256Mb-compatible DRAM process to reduce the fabrication cost. The graphics SoC is successfully demonstrated on two system evaluation boards running real-time applications ported with custom-designed MobileGL.