Spline large signal FET model

Abstract

In this thesis, a spline large-signal FET model was introduced. The model was developed to predict device’s characteristics without regard to the process of the device. The accuracy and robustness of the model was verified in three FET devices; FETs, HEMTs and MOSFETs. The thermal and trap effects were investigated, and the large signal model including thermal and trap effects was introduced. The model parameters were extracted from bias dependent pulsed I-V’s and S-parameters. The extraction method was very creative in a point that the trap and thermal effects were considered independently. The validity of the model is demonstrated using a commercially available MESFET device. Good agreements were shown in comparing the simulated small-signal S-parameters over wide bias range with measured data. Nonlinear simulation results of the device such as $P_{in}-P_{out}$, IMD3, and PAE were also matched very well with the measurements. A modified spline FET model was presented. The model was developed to have merits of simplicity in empirical model and accuracy in table-based model. Moreover, the extrapolability of the model was very useful in large power devices. The validity of the model was demonstrated using a commercially available HEMT device. Good agreements were shown in comparing measurements and simulations of pulsed I-V’s and S-parameters at various quiescent bias voltages. Also, the model accurately predicted load-pull measurement results including the output power and PAE. A spline large signal model for MOSFET devices was presented. A novel approach for the extraction of parasitic resistances is also described. This technique was developed to solve discrepancies between the measured I-V characteristic and the calculated one from integrations of the trans-conductance and the output conductance which were obtained using small signal S-parameters. The intrinsic device of the model represented by a parallel connection of current sources and charge sources and...