Nanosecond annealing using a pulsed green laser is proposed to activate the source/drain of top-tier pchannel metal-oxide-semiconductor field-effect transistors (pMOSFETs) while avoiding the degradation of preexisting bottom-tier devices. Localized high temperatures generated by green laser annealing (GLA) in the top-tier layer improve crystallinity and increase the activated boron concentration in the source/drain of top-tier pMOSFETs compared to conventional rapid thermal annealing (RTA). These improvements result in a reduction of sheet resistance (R-sh) and specific contact resistivity (rho(c)), thereby increasing the effective mobility (mu(eff)) of the top-tier Ge pMOSFETs by approximately 46%. As a result, heterogeneous 3-D sequential CFETs integrated using GLA achieve a high voltage gain (V-gain) of 68 V/V.