Low power synthesis problems in system-on-chip designs

Abstract

This thesis addresses four important synthesis problems with an objective of minimizing power consumption in system-on-chip (SoC) design. (1) Scheduling and binding problem for power minimization: We solve the problem efficiently by formulating it into the problem of finding a maximum flow of minimum cost in a network; (2) Interconnect synthesis problem with the consideration of coupled transition activity: We solve the problem by simultaneously formulating and solving the following two issues in an integrated fashion: binding data transfers to buses and determining a (physical) order of lines in each bus; (3) Bus encoding with crosstalk delay elimination problem: We solve the problem by analyzing, formulating, and solving the problem of minimizing a weighted sum of the self transition and cross-coupled transition activities on bus; (4) Memory optimization problem for energy minimization: We minimize the energy consumption by scheduling memory accesses and binding memories simultaneously, so that the use of standby mode in memories are maximized. A set of extensive experimental data is provided to confirm the effectiveness of the proposed approaches.