Multi-acess memory system for image processing

Abstract

This thesis considers a memory system which provides simultaneous accesses to pq image point of a block(p×q) or one subarray in the 8 directions (N, NE, E, SE, S, SW, W, and NW) in a 2-dimensional image array where p and q are integers. This memory system consists of a conversion circuitry, an address calculating circuitry, an address routing circuitry, a data routing circuitry, a memory module selecting circuitry, and m memory modules, where m is a prime number which is greater than pq. The address calculating circuitry computes pq addresses in parallel by using the differences of addresses of pq image points from the address of the base image point. This thesis also considers a memory system which provides simultaneous accesses to pq image points in a line-segment with an arbitrary degree in a 2-dimensional image array. The proposed memory system is analyzed to be faster than the previous memory system for the image processing operations, such as line detection with Hough transform, rotation, noise cleaning, or thinning.