DC Field | Value | Language |
---|---|---|
dc.contributor.advisor | Maeng, Seung-Ryoul | - |
dc.contributor.advisor | 맹승렬 | - |
dc.contributor.author | Lee, Moon-Sang | - |
dc.contributor.author | 이문상 | - |
dc.date.accessioned | 2011-12-13T05:21:31Z | - |
dc.date.available | 2011-12-13T05:21:31Z | - |
dc.date.issued | 2006 | - |
dc.identifier.uri | http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=254439&flag=dissertation | - |
dc.identifier.uri | http://hdl.handle.net/10203/32911 | - |
dc.description | 학위논문(박사) - 한국과학기술원 : 전산학전공, 2006.2, [ viii, 64 p. ] | - |
dc.description.abstract | User-level communication alleviates the software overhead of the communication subsystem by allowing applications to access the network interface directly. In user-level communication, a user process accesses a network interface using its own virtual address which should be translated to a physical address. A small caching structure which is similar to the TLB on the host processor has been used to cache the mappings between virtual and physical addresses on network interface memory. If a miss occurs in the caching structure, a network interface needs to retrieve a matching physical address from the host memory. To reduce the conflicts on the shared pages, existing techniques in processor cache design have been used. The caching structure on a network interface is generally managed by firmware software. In the case of a software managed cache, the cost of a lookup is increasing linearly with the degree of associativity since it can search only one cache entry at a time, and cache management for replacement becomes more complex and adds extra cost even for the case of a cache hit. Therefore, it is necessary to keep the translating mechanism as simple as possible while sustaining the high hit ratio to perform the address translation efficiently. In this thesis, we propose a new TLB architecture on the network interface. To exploit the spatial locality of application process and resolve the conflicts on the shared pages, the proposed architecture splits an original caching structure into as many partitions as the number of processors on the SMP system and assigns a separate partition to each of concurrent application processes. In addition, the architecture becomes aware of user contexts and switches the content of the caching structure according to the current user context. By resolving the conflicts from different user contexts, the proposed architecture can fully utilize the spatial and the temporal locality of application process. In this thesis, we also propo... | eng |
dc.language | eng | - |
dc.publisher | 한국과학기술원 | - |
dc.subject | Address Translation | - |
dc.subject | User-Level Communication | - |
dc.subject | Cluster System | - |
dc.subject | TLB | - |
dc.subject | 변환 참조 버퍼 | - |
dc.subject | 주소 변환 | - |
dc.subject | 사용자 수준 통신 | - |
dc.subject | 클러스터 시스템 | - |
dc.title | Address translation for user-level communication in SMP clusters | - |
dc.title.alternative | SMP 클러스터상에서 사용자 수준 통신을 위한 주소 변환에 관한 연구 | - |
dc.type | Thesis(Ph.D) | - |
dc.identifier.CNRN | 254439/325007 | - |
dc.description.department | 한국과학기술원 : 전산학전공, | - |
dc.identifier.uid | 000985262 | - |
dc.contributor.localauthor | Maeng, Seung-Ryoul | - |
dc.contributor.localauthor | 맹승렬 | - |
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.