(A) memory architecture for lock-free synchronization

Abstract

Lock-free synchronization has advantages over lock-based synchronization. Lock-free synchronization is deadlock-free and fault-tolerant, and eliminates interference between synchronization and the scheduler.In this thesis, we survey universal constructions of lock-free shared objects which automatically generates sequential implemations into lock-free implementations. However lock-free implementations are difficult to de-sign and to verify as correct. We propose intelligent memory a memory architecture for lock-free synchronization. We present an example implementation of intelligent memory and its programming model. Intelligent memory does not affect the existing cache coherence scheme and support any traditional atomic primitives by the CSP. Simulation results show that intelligent memory provides good performance compared with the lock based scheme and lock-free Synchronization scheme, and its performance is independent on process contention.