(An) Efficient DMA accelerator and memory mapping for supporting bank-level PIM

Abstract

One of the emerging issues in artificial intelligence workload is the lack of sufficient memory bandwidth during AI computations. To overcome this, bank-level PIM architectures, which integrate computing capabilities within DRAM banks to maximize memory bandwidth efficiency, have started to appear as proof of concept (POC) or have begun to be commercialized. Manufacturers of bank-level PIMs have made their products compatible with existing systems without requiring hardware changes to processors (CPU or GPU), but this compatibility introduces several inefficiencies. This thesis analyzes commercially available bank-level PIM, identifying performance degradation in data movement between DRAM and bank-level PIM. To address this, the thesis proposes memory mapping, direct memory access accelerators, and scheduling algorithms.