Hardware accelerator with output-bit-serial multiplication of data from MSB to LSB높은 자리부터 낮은 자리 순서로 출력을 생성하는 데이터 곱셈을 이용한 하드웨어 가속기
A hardware accelerator is one of the key modules to operate a Deep Neural Network (DNN) in edge devices. Hardware accelerators optimize the order and mechanism of data processing to fully utilize limited resources of the edge devices. Especially, optimizing the order of processing maximizes the number of data reuse and minimizes the movement of data, which consumes relatively large energy. Data processing can be implemented in many different orders, and also can be unrolled and tiled. In this paper, a hardware accelerator specialized in manipulations of data processing order in data bit-width and input channel directions is discussed.
- Advisors
- 정완영researcher
- Description
- 한국과학기술원 :전기및전자공학부,
- Publisher
- 한국과학기술원
- Issue Date
- 2022
- Identifier
- 325007
- Language
- eng
- Description
학위논문(석사) - 한국과학기술원 : 전기및전자공학부, 2022.2,[iv, 39 p. :]
- Keywords
하드웨어 가속기▼a깊은 인공신경망▼a데이터 처리 순서▼a데이터 타일링▼a루프 풀기▼a데이터의 비트폭; Hardware accelerator▼aDeep neural network▼aOrder of data processing▼aTiling▼aLoop-unrolling▼aData bit-width
- Appears in Collection
- EE-Theses_Master(석사논문)
- Files in This Item
- There are no files associated with this item.
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.