Hardware accelerator with output-bit-serial multiplication of data from MSB to LSB

Abstract

A hardware accelerator is one of the key modules to operate a Deep Neural Network (DNN) in edge devices. Hardware accelerators optimize the order and mechanism of data processing to fully utilize limited resources of the edge devices. Especially, optimizing the order of processing maximizes the number of data reuse and minimizes the movement of data, which consumes relatively large energy. Data processing can be implemented in many different orders, and also can be unrolled and tiled. In this paper, a hardware accelerator specialized in manipulations of data processing order in data bit-width and input channel directions is discussed.