High-Pressure Deuterium Annealing for Trap Passivation for a 3-D Integrated Structure

Abstract

High-pressure deuterium annealing (HPDA) and forming gas annealing (FGA) were applied to monolithically and vertically integrated MOSFETs with a 3-D architecture of one over the other. An overlying poly-Si thin-film transistor (TFT) is positioned over an underlying MOSFET onto a wafer of silicon-on-insulator (SOI). The effects of HPDA and FGA on these double-stacked MOSFETs were quantitatively analyzed by extracting the interface trap density (N-it) from dc I-V characteristics and border trap density (N-bt) through low-frequency noise (LFN) measurements. The performance index parameters, such as subthreshold swing (SS) and on-state current (I-ON), were also comparatively analyzed. It has been confirmed that, for the superjacent MOSFET, HPDA reduced N-it by 250% and N-bt by 92% compared to FGA. Additionally, for the subjacent MOSFET, HPDA decreased N-it by 15% and Nbt by 32% compared to FGA.